From f9a4bb78dadc12c7c1e604c6f17b63a71305c2ca Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Fri, 30 Sep 2011 22:18:45 +0000 Subject: [PATCH] Compute lists of super-classes in CodeGenRegisterClass. Use these lists instead of computing them on the fly in RegisterInfoEmitter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140895 91177308-0d34-0410-b5e6-96231b3b80d8 --- utils/TableGen/CodeGenRegisters.cpp | 10 +++++ utils/TableGen/CodeGenRegisters.h | 14 +++++++ utils/TableGen/RegisterInfoEmitter.cpp | 58 +++++++++----------------- 3 files changed, 43 insertions(+), 39 deletions(-) diff --git a/utils/TableGen/CodeGenRegisters.cpp b/utils/TableGen/CodeGenRegisters.cpp index c7124950124..35f247a2e38 100644 --- a/utils/TableGen/CodeGenRegisters.cpp +++ b/utils/TableGen/CodeGenRegisters.cpp @@ -414,6 +414,16 @@ computeSubClasses(ArrayRef RegClasses) { for (unsigned s = rci - 1; s && RC.hasSubClass(RegClasses[s - 1]); --s) RC.SubClasses.set(s - 1); } + + // Compute the SuperClasses lists from the SubClasses vectors. + for (unsigned rci = 0; rci != RegClasses.size(); ++rci) { + const BitVector &SC = RegClasses[rci]->getSubClasses(); + for (int s = SC.find_first(); s >= 0; s = SC.find_next(s)) { + if (unsigned(s) == rci) + continue; + RegClasses[s]->SuperClasses.push_back(RegClasses[rci]); + } + } } //===----------------------------------------------------------------------===// diff --git a/utils/TableGen/CodeGenRegisters.h b/utils/TableGen/CodeGenRegisters.h index ae8f0d4abdf..74cf4127a32 100644 --- a/utils/TableGen/CodeGenRegisters.h +++ b/utils/TableGen/CodeGenRegisters.h @@ -90,6 +90,9 @@ namespace llvm { std::vector > AltOrders; // Bit mask of sub-classes including this, indexed by their EnumValue. BitVector SubClasses; + // List of super-classes, topologocally ordered to have the larger classes + // first. This is the same as sorting by EnumValue. + SmallVector SuperClasses; public: Record *TheDef; unsigned EnumValue; @@ -128,6 +131,17 @@ namespace llvm { // bool hasSubClass(const CodeGenRegisterClass *RC) const; + // getSubClasses - Returns a constant BitVector of subclasses indexed by + // EnumValue. + // The SubClasses vector includs an entry for this class. + const BitVector &getSubClasses() const { return SubClasses; }; + + // getSuperClasses - Returns a list of super classes ordered by EnumValue. + // The array does not include an entry for this class. + ArrayRef getSuperClasses() const { + return SuperClasses; + } + // Returns an ordered list of class members. // The order of registers is the same as in the .td file. // No = 0 is the default allocation order, No = 1 is the first alternative. diff --git a/utils/TableGen/RegisterInfoEmitter.cpp b/utils/TableGen/RegisterInfoEmitter.cpp index bc67de9cb03..b784e738e07 100644 --- a/utils/TableGen/RegisterInfoEmitter.cpp +++ b/utils/TableGen/RegisterInfoEmitter.cpp @@ -527,9 +527,10 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, OS << " " << RegisterClasses[i]->getName() << "Class\t" << RegisterClasses[i]->getName() << "RegClass;\n"; - std::map > SuperClassMap; std::map > SuperRegClassMap; - OS << "\n"; + + OS << "\n static const TargetRegisterClass* const " + << "NullRegClasses[] = { NULL };\n\n"; unsigned NumSubRegIndices = RegBank.getSubRegIndices().size(); @@ -603,10 +604,6 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, OS << (!Empty ? ", " : "") << "NULL"; OS << "\n };\n\n"; } - } else { - // No subregindices in this target - OS << " static const TargetRegisterClass* const " - << "NullRegClasses[] = { NULL };\n\n"; } // Emit the sub-classes array for each RegisterClass @@ -632,46 +629,26 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, if (!Empty) OS << ", "; OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass"; Empty = false; - - std::map >::iterator SCMI = - SuperClassMap.find(rc2); - if (SCMI == SuperClassMap.end()) { - SuperClassMap.insert(std::make_pair(rc2, std::set())); - SCMI = SuperClassMap.find(rc2); - } - SCMI->second.insert(rc); } OS << (!Empty ? ", " : "") << "NULL"; OS << "\n };\n\n"; } + // Emit NULL terminated super-class lists. for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { const CodeGenRegisterClass &RC = *RegisterClasses[rc]; + ArrayRef Supers = RC.getSuperClasses(); - // Give the register class a legal C name if it's anonymous. - std::string Name = RC.TheDef->getName(); + // Skip classes without supers. We can reuse NullRegClasses. + if (Supers.empty()) + continue; - OS << " // " << Name - << " Register Class super-classes...\n" - << " static const TargetRegisterClass* const " - << Name << "Superclasses[] = {\n "; - - bool Empty = true; - std::map >::iterator I = - SuperClassMap.find(rc); - if (I != SuperClassMap.end()) { - for (std::set::iterator II = I->second.begin(), - EE = I->second.end(); II != EE; ++II) { - const CodeGenRegisterClass &RC2 = *RegisterClasses[*II]; - if (!Empty) OS << ", "; - OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass"; - Empty = false; - } - } - - OS << (!Empty ? ", " : "") << "NULL"; - OS << "\n };\n\n"; + OS << " static const TargetRegisterClass* const " + << RC.getName() << "Superclasses[] = {\n"; + for (unsigned i = 0; i != Supers.size(); ++i) + OS << " &" << getQualifiedName(Supers[i]->TheDef) << "RegClass,\n"; + OS << " NULL\n };\n\n"; } // Emit methods. @@ -682,9 +659,12 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, << Target.getName() << "MCRegisterClasses[" << RC.getName() + "RegClassID" << "], " << RC.getName() + "VTs" << ", " - << RC.getName() + "Subclasses" << ", " - << RC.getName() + "Superclasses" << ", " - << (NumSubRegIndices ? RC.getName() + "Sub" : std::string("Null")) + << RC.getName() + "Subclasses" << ", "; + if (RC.getSuperClasses().empty()) + OS << "NullRegClasses, "; + else + OS << RC.getName() + "Superclasses, "; + OS << (NumSubRegIndices ? RC.getName() + "Sub" : std::string("Null")) << "RegClasses, " << (NumSubRegIndices ? RC.getName() + "Super" : std::string("Null")) << "RegClasses"