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Replace sra with srl if a single sign bit is required

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E.g. (and (sra (i32 x) 31) 2) -> (and (srl (i32 x) 30) 2).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192884 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Sandiford
2013-10-17 11:16:57 +00:00
parent 888cbad774
commit f9a5e40b90
3 changed files with 30 additions and 8 deletions
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test/CodeGen/PowerPC/rlwimi-and.ll
+4 -5
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@@ -28,12 +28,11 @@ codeRepl17: ; preds = %codeRepl4
store i16 %rvml38.sroa.0.0.insert.insert, i16* undef, align 2
unreachable
; FIXME: the SLWI could be folded into the RLWIMI to give a rotate of 8.
; CHECK: @test
; CHECK-DAG: slwi [[R1:[0-9]+]],
; CHECK-DAG: rlwinm [[R2:[0-9]+]],
; CHECK-DAG: srawi [[R3:[0-9]+]], [[R1]]
; CHECK-DAG: rlwinm [[R4:[0-9]+]], [[R3]], 0, 23, 23
; CHECK: rlwimi [[R4]], [[R2]], 0,
; CHECK-DAG: slwi [[R1:[0-9]+]], {{[0-9]+}}, 31
; CHECK-DAG: rlwinm [[R2:[0-9]+]], {{[0-9]+}}, 0, 31, 31
; CHECK: rlwimi [[R2]], [[R1]], 9, 23, 23
codeRepl29: ; preds = %codeRepl1
unreachable