mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-17 20:29:31 +00:00
The last pieces needed for loading arbitrary
precision integers. This won't actually work (and most of the code is dead) unless the new legalization machinery is turned on. While there, I rationalized the handling of i1, and removed some bogus (and unused) sextload patterns. For i1, this could result in microscopically better code for some architectures (not X86). It might also result in worse code if annotating with AssertZExt nodes turns out to be more harmful than helpful. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46280 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Duncan Sands
parent
1eed950d7c
commit
f9c98e650d
@ -1820,76 +1820,188 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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return Op.ResNo ? Tmp4 : Tmp3;
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} else {
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MVT::ValueType SrcVT = LD->getLoadedVT();
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switch (TLI.getLoadXAction(ExtType, SrcVT)) {
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default: assert(0 && "This action is not supported yet!");
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case TargetLowering::Promote:
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assert(SrcVT == MVT::i1 &&
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"Can only promote extending LOAD from i1 -> i8!");
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Result = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
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LD->getSrcValue(), LD->getSrcValueOffset(),
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MVT::i8, LD->isVolatile(), LD->getAlignment());
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Tmp1 = Result.getValue(0);
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Tmp2 = Result.getValue(1);
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break;
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case TargetLowering::Custom:
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isCustom = true;
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// FALLTHROUGH
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case TargetLowering::Legal:
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Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
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Tmp1 = Result.getValue(0);
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Tmp2 = Result.getValue(1);
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if (isCustom) {
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Tmp3 = TLI.LowerOperation(Result, DAG);
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if (Tmp3.Val) {
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Tmp1 = LegalizeOp(Tmp3);
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Tmp2 = LegalizeOp(Tmp3.getValue(1));
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}
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unsigned SrcWidth = MVT::getSizeInBits(SrcVT);
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int SVOffset = LD->getSrcValueOffset();
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unsigned Alignment = LD->getAlignment();
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bool isVolatile = LD->isVolatile();
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if (SrcWidth != MVT::getStoreSizeInBits(SrcVT) &&
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// Some targets pretend to have an i1 loading operation, and actually
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// load an i8. This trick is correct for ZEXTLOAD because the top 7
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// bits are guaranteed to be zero; it helps the optimizers understand
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// that these bits are zero. It is also useful for EXTLOAD, since it
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// tells the optimizers that those bits are undefined. It would be
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// nice to have an effective generic way of getting these benefits...
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// Until such a way is found, don't insist on promoting i1 here.
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(SrcVT != MVT::i1 ||
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TLI.getLoadXAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
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// Promote to a byte-sized load if not loading an integral number of
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// bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
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unsigned NewWidth = MVT::getStoreSizeInBits(SrcVT);
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MVT::ValueType NVT = MVT::getIntegerType(NewWidth);
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SDOperand Ch;
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// The extra bits are guaranteed to be zero, since we stored them that
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// way. A zext load from NVT thus automatically gives zext from SrcVT.
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ISD::LoadExtType NewExtType =
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ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
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Result = DAG.getExtLoad(NewExtType, Node->getValueType(0),
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Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
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NVT, isVolatile, Alignment);
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Ch = Result.getValue(1); // The chain.
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if (ExtType == ISD::SEXTLOAD)
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// Having the top bits zero doesn't help when sign extending.
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Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
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Result, DAG.getValueType(SrcVT));
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else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
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// All the top bits are guaranteed to be zero - inform the optimizers.
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Result = DAG.getNode(ISD::AssertZext, Result.getValueType(), Result,
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DAG.getValueType(SrcVT));
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Tmp1 = LegalizeOp(Result);
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Tmp2 = LegalizeOp(Ch);
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} else if (SrcWidth & (SrcWidth - 1)) {
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// If not loading a power-of-2 number of bits, expand as two loads.
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assert(MVT::isExtendedVT(SrcVT) && !MVT::isVector(SrcVT) &&
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"Unsupported extload!");
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unsigned RoundWidth = 1 << Log2_32(SrcWidth);
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assert(RoundWidth < SrcWidth);
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unsigned ExtraWidth = SrcWidth - RoundWidth;
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assert(ExtraWidth < RoundWidth);
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assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
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"Load size not an integral number of bytes!");
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MVT::ValueType RoundVT = MVT::getIntegerType(RoundWidth);
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MVT::ValueType ExtraVT = MVT::getIntegerType(ExtraWidth);
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SDOperand Lo, Hi, Ch;
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unsigned IncrementSize;
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if (TLI.isLittleEndian()) {
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// EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
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// Load the bottom RoundWidth bits.
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Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
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LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
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Alignment);
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// Load the remaining ExtraWidth bits.
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IncrementSize = RoundWidth / 8;
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Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
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DAG.getIntPtrConstant(IncrementSize));
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Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
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LD->getSrcValue(), SVOffset + IncrementSize,
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ExtraVT, isVolatile,
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MinAlign(Alignment, IncrementSize));
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// Build a factor node to remember that this load is independent of the
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// other one.
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Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
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Hi.getValue(1));
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// Move the top bits to the right place.
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Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
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DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
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// Join the hi and lo parts.
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Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
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} else {
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// If this is an unaligned load and the target doesn't support it,
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// expand it.
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if (!TLI.allowsUnalignedMemoryAccesses()) {
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unsigned ABIAlignment = TLI.getTargetData()->
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getABITypeAlignment(MVT::getTypeForValueType(LD->getLoadedVT()));
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if (LD->getAlignment() < ABIAlignment){
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Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
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TLI);
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Tmp1 = Result.getOperand(0);
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Tmp2 = Result.getOperand(1);
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Tmp1 = LegalizeOp(Tmp1);
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Tmp2 = LegalizeOp(Tmp2);
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// Big endian - avoid unaligned loads.
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// EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
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// Load the top RoundWidth bits.
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Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
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LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
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Alignment);
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// Load the remaining ExtraWidth bits.
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IncrementSize = RoundWidth / 8;
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Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
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DAG.getIntPtrConstant(IncrementSize));
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Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
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LD->getSrcValue(), SVOffset + IncrementSize,
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ExtraVT, isVolatile,
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MinAlign(Alignment, IncrementSize));
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// Build a factor node to remember that this load is independent of the
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// other one.
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Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
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Hi.getValue(1));
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// Move the top bits to the right place.
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Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
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DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
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// Join the hi and lo parts.
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Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
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}
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Tmp1 = LegalizeOp(Result);
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Tmp2 = LegalizeOp(Ch);
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} else {
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switch (TLI.getLoadXAction(ExtType, SrcVT)) {
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default: assert(0 && "This action is not supported yet!");
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case TargetLowering::Custom:
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isCustom = true;
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// FALLTHROUGH
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case TargetLowering::Legal:
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Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
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Tmp1 = Result.getValue(0);
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Tmp2 = Result.getValue(1);
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if (isCustom) {
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Tmp3 = TLI.LowerOperation(Result, DAG);
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if (Tmp3.Val) {
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Tmp1 = LegalizeOp(Tmp3);
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Tmp2 = LegalizeOp(Tmp3.getValue(1));
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}
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} else {
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// If this is an unaligned load and the target doesn't support it,
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// expand it.
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if (!TLI.allowsUnalignedMemoryAccesses()) {
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unsigned ABIAlignment = TLI.getTargetData()->
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getABITypeAlignment(MVT::getTypeForValueType(LD->getLoadedVT()));
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if (LD->getAlignment() < ABIAlignment){
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Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
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TLI);
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Tmp1 = Result.getOperand(0);
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Tmp2 = Result.getOperand(1);
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Tmp1 = LegalizeOp(Tmp1);
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Tmp2 = LegalizeOp(Tmp2);
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}
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}
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}
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}
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break;
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case TargetLowering::Expand:
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// f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
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if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
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SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
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LD->getSrcValueOffset(),
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LD->isVolatile(), LD->getAlignment());
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Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
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Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
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Tmp2 = LegalizeOp(Load.getValue(1));
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break;
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case TargetLowering::Expand:
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// f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
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if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
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SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
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LD->getSrcValueOffset(),
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LD->isVolatile(), LD->getAlignment());
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Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
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Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
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Tmp2 = LegalizeOp(Load.getValue(1));
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break;
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}
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assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
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// Turn the unsupported load into an EXTLOAD followed by an explicit
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// zero/sign extend inreg.
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Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
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Tmp1, Tmp2, LD->getSrcValue(),
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LD->getSrcValueOffset(), SrcVT,
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LD->isVolatile(), LD->getAlignment());
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SDOperand ValRes;
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if (ExtType == ISD::SEXTLOAD)
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ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
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Result, DAG.getValueType(SrcVT));
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else
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ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
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Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
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Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
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break;
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}
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assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
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// Turn the unsupported load into an EXTLOAD followed by an explicit
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// zero/sign extend inreg.
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Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
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Tmp1, Tmp2, LD->getSrcValue(),
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LD->getSrcValueOffset(), SrcVT,
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LD->isVolatile(), LD->getAlignment());
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SDOperand ValRes;
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if (ExtType == ISD::SEXTLOAD)
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ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
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Result, DAG.getValueType(SrcVT));
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else
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ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
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Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
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Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
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break;
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}
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// Since loads produce two values, make sure to remember that we legalized
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// both of them.
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AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
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@ -133,6 +133,9 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
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// ARM does not have f32 extending load.
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setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand);
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// ARM does not have i1 sign extending load.
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setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
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// ARM supports all 4 flavors of integer indexed load / store.
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for (unsigned im = (unsigned)ISD::PRE_INC;
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im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
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@ -37,9 +37,9 @@ IA64TargetLowering::IA64TargetLowering(TargetMachine &TM)
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setLoadXAction(ISD::EXTLOAD , MVT::i1 , Promote);
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setLoadXAction(ISD::ZEXTLOAD , MVT::i1 , Expand);
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setLoadXAction(ISD::ZEXTLOAD , MVT::i1 , Promote);
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setLoadXAction(ISD::SEXTLOAD , MVT::i1 , Expand);
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setLoadXAction(ISD::SEXTLOAD , MVT::i1 , Promote);
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setLoadXAction(ISD::SEXTLOAD , MVT::i8 , Expand);
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setLoadXAction(ISD::SEXTLOAD , MVT::i16 , Expand);
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setLoadXAction(ISD::SEXTLOAD , MVT::i32 , Expand);
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@ -52,9 +52,9 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
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addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
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// PowerPC has an i16 but no i8 (or i1) SEXTLOAD
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setLoadXAction(ISD::SEXTLOAD, MVT::i1, Expand);
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setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
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setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand);
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setTruncStoreAction(MVT::f64, MVT::f32, Expand);
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// PowerPC has pre-inc load and store's.
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@ -138,7 +138,10 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
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// Turn FP extload into load/fextend
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setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand);
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// Sparc doesn't have i1 sign extending load
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setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
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// Custom legalize GlobalAddress nodes into LO/HI parts.
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setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
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setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
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@ -80,7 +80,7 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
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if (Subtarget->is64Bit())
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addRegisterClass(MVT::i64, X86::GR64RegisterClass);
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setLoadXAction(ISD::SEXTLOAD, MVT::i1, Expand);
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setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
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// We don't accept any truncstore of integer registers.
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setTruncStoreAction(MVT::i64, MVT::i32, Expand);
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@ -61,7 +61,6 @@ def i64immSExt8 : PatLeaf<(i64 imm), [{
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return (int64_t)N->getValue() == (int8_t)N->getValue();
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}]>;
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def sextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (sextloadi1 node:$ptr))>;
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def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
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def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
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def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
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@ -1177,8 +1176,7 @@ def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
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def : Pat<(parallel (X86cmp GR64:$src1, 0), (implicit EFLAGS)),
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(TEST64rr GR64:$src1, GR64:$src1)>;
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// {s|z}extload bool -> {s|z}extload byte
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def : Pat<(sextloadi64i1 addr:$src), (MOVSX64rm8 addr:$src)>;
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// zextload bool -> zextload byte
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def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
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// extload
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@ -226,8 +226,6 @@ def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
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def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
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def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
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def sextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (sextloadi1 node:$ptr))>;
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def sextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (sextloadi1 node:$ptr))>;
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def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
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def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
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def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
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@ -2608,9 +2606,7 @@ def : Pat<(parallel (X86cmp GR16:$src1, 0), (implicit EFLAGS)),
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def : Pat<(parallel (X86cmp GR32:$src1, 0), (implicit EFLAGS)),
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(TEST32rr GR32:$src1, GR32:$src1)>;
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// {s|z}extload bool -> {s|z}extload byte
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def : Pat<(sextloadi16i1 addr:$src), (MOVSX16rm8 addr:$src)>;
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def : Pat<(sextloadi32i1 addr:$src), (MOVSX32rm8 addr:$src)>;
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// zextload bool -> zextload byte
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def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
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def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
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def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
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