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The Thumb2 Ld, St, and Preload instructions with the i12 forms should have its Inst{23}

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be specified as '1' (add = TRUE).

Also add a utility function for Thumb2.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129377 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen 2011-04-12 18:48:00 +00:00
parent e1b43c3b40
commit f9ce2cba42
3 changed files with 18 additions and 1 deletions
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3
lib/Target/ARM/ARMInstrThumb2.td
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@ -845,6 +845,7 @@ multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
let Inst{15-12} = Rt;
bits<17> addr;
let addr{12} = 1; // add = TRUE
let Inst{19-16} = addr{16-13}; // Rn
let Inst{23} = addr{12}; // U
let Inst{11-0} = addr{11-0}; // imm
@ -925,6 +926,7 @@ multiclass T2I_st<bits<2> opcod, string opc,
let Inst{15-12} = Rt;
bits<17> addr;
let addr{12} = 1; // add = TRUE
let Inst{19-16} = addr{16-13}; // Rn
let Inst{23} = addr{12}; // U
let Inst{11-0} = addr{11-0}; // imm
@ -1522,6 +1524,7 @@ multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> {
let Inst{15-12} = 0b1111;
bits<17> addr;
let addr{12} = 1; // add = TRUE
let Inst{19-16} = addr{16-13}; // Rn
let Inst{23} = addr{12}; // U
let Inst{11-0} = addr{11-0}; // imm12

2
lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
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@ -108,6 +108,8 @@ static inline bool IsGPR(unsigned RegClass) {
// Utilities for 32-bit Thumb instructions.
static inline bool BadReg(uint32_t n) { return n == 13 || n == 15; }
// Extract imm4: Inst{19-16}.
static inline unsigned getImm4(uint32_t insn) {
return slice(insn, 19, 16);

14
test/MC/Disassembler/ARM/thumb-tests.txt
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@ -171,7 +171,16 @@
0x5d 0xf8 0x34 0x40
# CHECK: ldr.w r5, [r6, #30]
0x56 0xf8 0x1e 0x56
0xd6 0xf8 0x1e 0x50
# CHECK: ldrh.w r5, [r6, #30]
0xb6 0xf8 0x1e 0x50
# CHECK: ldrt r5, [r6, #30]
0x56 0xf8 0x1e 0x5e
# CHECK: ldr r5, [r6, #-30]
0x56 0xf8 0x1e 0x5c
# CHECK: sel r7, r3, r5
0xa3 0xfa 0x85 0xf7
@ -197,6 +206,9 @@
# CHECK: pld [pc, #-16]
0x1f 0xf8 0x10 0xf0
# CHECK: pld [r5, #30]
0x95 0xf8 0x1e 0xf0
# CHECK: stc2 p12, cr15, [r9], {137}
0x89 0xfc 0x89 0xfc