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ARM & AArch64: merge NEON absolute compare intrinsics
There was an extremely confusing proliferation of LLVM intrinsics to implement the vacge & vacgt instructions. This combines them all into two polymorphic intrinsics, shared across both backends. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200768 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover
parent
8753ba91d2
commit
f9ced85e49
@ -155,6 +155,10 @@ class Neon_CvtFPToFx_Intrinsic
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class Neon_CvtFPtoInt_1Arg_Intrinsic
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: Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
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class Neon_Compare_Intrinsic
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: Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty, LLVMMatchType<1>],
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[IntrNoMem]>;
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// The table operands for VTBL and VTBX consist of 1 to 4 v8i8 vectors.
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// Besides the table, VTBL has one other v8i8 argument and VTBX has two.
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// Overall, the classes range from 2 to 6 v8i8 arguments.
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@ -224,18 +228,8 @@ def int_arm_neon_vqsubu : Neon_2Arg_Intrinsic;
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def int_arm_neon_vrsubhn : Neon_2Arg_Narrow_Intrinsic;
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// Vector Absolute Compare.
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def int_arm_neon_vacged : Intrinsic<[llvm_v2i32_ty],
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[llvm_v2f32_ty, llvm_v2f32_ty],
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[IntrNoMem]>;
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def int_arm_neon_vacgeq : Intrinsic<[llvm_v4i32_ty],
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[llvm_v4f32_ty, llvm_v4f32_ty],
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[IntrNoMem]>;
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def int_arm_neon_vacgtd : Intrinsic<[llvm_v2i32_ty],
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[llvm_v2f32_ty, llvm_v2f32_ty],
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[IntrNoMem]>;
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def int_arm_neon_vacgtq : Intrinsic<[llvm_v4i32_ty],
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[llvm_v4f32_ty, llvm_v4f32_ty],
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[IntrNoMem]>;
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def int_arm_neon_vacge : Neon_Compare_Intrinsic;
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def int_arm_neon_vacgt : Neon_Compare_Intrinsic;
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// Vector Absolute Differences.
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def int_arm_neon_vabds : Neon_2Arg_Intrinsic;
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@ -210,9 +210,7 @@ multiclass NeonI_3VSame_BHSD_sizes<bit u, bits<5> opcode,
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// Multiclass NeonI_3VSame_SD_sizes: Operand types are floating point types,
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// but Result types can be integer or floating point types.
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multiclass NeonI_3VSame_SD_sizes<bit u, bit size, bits<5> opcode,
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string asmop, SDPatternOperator opnode2S,
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SDPatternOperator opnode4S,
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SDPatternOperator opnode2D,
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string asmop, SDPatternOperator opnode,
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ValueType ResTy2S, ValueType ResTy4S,
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ValueType ResTy2D, bit Commutable = 0> {
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let isCommutable = Commutable in {
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@ -220,21 +218,21 @@ multiclass NeonI_3VSame_SD_sizes<bit u, bit size, bits<5> opcode,
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(outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
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asmop # "\t$Rd.2s, $Rn.2s, $Rm.2s",
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[(set (ResTy2S VPR64:$Rd),
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(ResTy2S (opnode2S (v2f32 VPR64:$Rn), (v2f32 VPR64:$Rm))))],
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(ResTy2S (opnode (v2f32 VPR64:$Rn), (v2f32 VPR64:$Rm))))],
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NoItinerary>;
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def _4S : NeonI_3VSame<0b1, u, {size, 0b0}, opcode,
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(outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
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asmop # "\t$Rd.4s, $Rn.4s, $Rm.4s",
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[(set (ResTy4S VPR128:$Rd),
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(ResTy4S (opnode4S (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rm))))],
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(ResTy4S (opnode (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rm))))],
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NoItinerary>;
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def _2D : NeonI_3VSame<0b1, u, {size, 0b1}, opcode,
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(outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
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asmop # "\t$Rd.2d, $Rn.2d, $Rm.2d",
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[(set (ResTy2D VPR128:$Rd),
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(ResTy2D (opnode2D (v2f64 VPR128:$Rn), (v2f64 VPR128:$Rm))))],
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(ResTy2D (opnode (v2f64 VPR128:$Rn), (v2f64 VPR128:$Rm))))],
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NoItinerary>;
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}
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}
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@ -248,19 +246,19 @@ multiclass NeonI_3VSame_SD_sizes<bit u, bit size, bits<5> opcode,
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// Vector Add (Integer and Floating-Point)
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defm ADDvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b10000, "add", add, 1>;
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defm FADDvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11010, "fadd", fadd, fadd, fadd,
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defm FADDvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11010, "fadd", fadd,
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v2f32, v4f32, v2f64, 1>;
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// Vector Sub (Integer and Floating-Point)
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defm SUBvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b10000, "sub", sub, 0>;
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defm FSUBvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11010, "fsub", fsub, fsub, fsub,
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defm FSUBvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11010, "fsub", fsub,
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v2f32, v4f32, v2f64, 0>;
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// Vector Multiply (Integer and Floating-Point)
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defm MULvvv : NeonI_3VSame_BHS_sizes<0b0, 0b10011, "mul", mul, 1>;
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defm FMULvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11011, "fmul", fmul, fmul, fmul,
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defm FMULvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11011, "fmul", fmul,
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v2f32, v4f32, v2f64, 1>;
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// Vector Multiply (Polynomial)
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@ -359,7 +357,7 @@ def : Pat<(v2f64 (fma (fneg VPR128:$Rn), VPR128:$Rm, VPR128:$Ra)),
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// Vector Divide (Floating-Point)
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defm FDIVvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11111, "fdiv", fdiv, fdiv, fdiv,
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defm FDIVvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11111, "fdiv", fdiv,
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v2f32, v4f32, v2f64, 0>;
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// Vector Bitwise Operations
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@ -610,19 +608,15 @@ defm SABDvvv : NeonI_3VSame_BHS_sizes<0b0, 0b01110, "sabd", int_arm_neon_vabds,
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// Vector Absolute Difference (Floating Point)
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defm FABDvvv: NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11010, "fabd",
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int_arm_neon_vabds, int_arm_neon_vabds,
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int_arm_neon_vabds, v2f32, v4f32, v2f64, 0>;
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// Vector Reciprocal Step (Floating Point)
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defm FRECPSvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11111, "frecps",
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int_arm_neon_vrecps, int_arm_neon_vrecps,
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int_arm_neon_vrecps,
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v2f32, v4f32, v2f64, 0>;
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// Vector Reciprocal Square Root Step (Floating Point)
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defm FRSQRTSvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11111, "frsqrts",
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int_arm_neon_vrsqrts,
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int_arm_neon_vrsqrts,
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int_arm_neon_vrsqrts,
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v2f32, v4f32, v2f64, 0>;
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@ -795,18 +789,15 @@ defm CMLTvvi : NeonI_cmpz_sizes<0b0, 0b01010, "cmlt", SETLT>;
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// Vector Compare Mask Equal (Floating Point)
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let isCommutable =1 in {
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defm FCMEQvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11100, "fcmeq", Neon_cmeq,
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Neon_cmeq, Neon_cmeq,
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v2i32, v4i32, v2i64, 0>;
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}
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// Vector Compare Mask Greater Than Or Equal (Floating Point)
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defm FCMGEvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11100, "fcmge", Neon_cmge,
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Neon_cmge, Neon_cmge,
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v2i32, v4i32, v2i64, 0>;
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// Vector Compare Mask Greater Than (Floating Point)
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defm FCMGTvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11100, "fcmgt", Neon_cmgt,
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Neon_cmgt, Neon_cmgt,
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v2i32, v4i32, v2i64, 0>;
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// Vector Compare Mask Less Than Or Equal (Floating Point)
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@ -878,14 +869,12 @@ defm FCMLTvvi : NeonI_fpcmpz_sizes<0b0, 0b1, 0b01110, "fcmlt", SETLT>;
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// Vector Absolute Compare Mask Greater Than Or Equal (Floating Point)
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defm FACGEvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11101, "facge",
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int_arm_neon_vacged, int_arm_neon_vacgeq,
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int_aarch64_neon_vacgeq,
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int_arm_neon_vacge,
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v2i32, v4i32, v2i64, 0>;
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// Vector Absolute Compare Mask Greater Than (Floating Point)
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defm FACGTvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11101, "facgt",
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int_arm_neon_vacgtd, int_arm_neon_vacgtq,
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int_aarch64_neon_vacgtq,
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int_arm_neon_vacgt,
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v2i32, v4i32, v2i64, 0>;
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// Vector Absolute Compare Mask Less Than Or Equal (Floating Point)
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@ -964,25 +953,21 @@ defm UMINvvv : NeonI_3VSame_BHS_sizes<0b1, 0b01101, "umin", int_arm_neon_vminu,
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// Vector Maximum (Floating Point)
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defm FMAXvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11110, "fmax",
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int_arm_neon_vmaxs, int_arm_neon_vmaxs,
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int_arm_neon_vmaxs, v2f32, v4f32, v2f64, 1>;
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int_arm_neon_vmaxs,
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v2f32, v4f32, v2f64, 1>;
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// Vector Minimum (Floating Point)
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defm FMINvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11110, "fmin",
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int_arm_neon_vmins, int_arm_neon_vmins,
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int_arm_neon_vmins, v2f32, v4f32, v2f64, 1>;
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int_arm_neon_vmins,
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v2f32, v4f32, v2f64, 1>;
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// Vector maxNum (Floating Point) - prefer a number over a quiet NaN)
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defm FMAXNMvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11000, "fmaxnm",
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int_aarch64_neon_vmaxnm,
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int_aarch64_neon_vmaxnm,
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int_aarch64_neon_vmaxnm,
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v2f32, v4f32, v2f64, 1>;
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// Vector minNum (Floating Point) - prefer a number over a quiet NaN)
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defm FMINNMvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11000, "fminnm",
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int_aarch64_neon_vminnm,
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int_aarch64_neon_vminnm,
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int_aarch64_neon_vminnm,
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v2f32, v4f32, v2f64, 1>;
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@ -996,25 +981,19 @@ defm UMINPvvv : NeonI_3VSame_BHS_sizes<0b1, 0b10101, "uminp", int_arm_neon_vpmin
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// Vector Maximum Pairwise (Floating Point)
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defm FMAXPvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11110, "fmaxp",
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int_arm_neon_vpmaxs, int_arm_neon_vpmaxs,
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int_arm_neon_vpmaxs, v2f32, v4f32, v2f64, 1>;
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// Vector Minimum Pairwise (Floating Point)
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defm FMINPvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11110, "fminp",
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int_arm_neon_vpmins, int_arm_neon_vpmins,
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int_arm_neon_vpmins, v2f32, v4f32, v2f64, 1>;
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// Vector maxNum Pairwise (Floating Point) - prefer a number over a quiet NaN)
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defm FMAXNMPvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11000, "fmaxnmp",
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int_aarch64_neon_vpmaxnm,
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int_aarch64_neon_vpmaxnm,
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int_aarch64_neon_vpmaxnm,
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v2f32, v4f32, v2f64, 1>;
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// Vector minNum Pairwise (Floating Point) - prefer a number over a quiet NaN)
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defm FMINNMPvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11000, "fminnmp",
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int_aarch64_neon_vpminnm,
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int_aarch64_neon_vpminnm,
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int_aarch64_neon_vpminnm,
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v2f32, v4f32, v2f64, 1>;
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@ -1023,8 +1002,6 @@ defm ADDP : NeonI_3VSame_BHSD_sizes<0b0, 0b10111, "addp", int_arm_neon_vpadd, 1>
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// Vector Addition Pairwise (Floating Point)
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defm FADDP : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11010, "faddp",
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int_arm_neon_vpadd,
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int_arm_neon_vpadd,
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int_arm_neon_vpadd,
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v2f32, v4f32, v2f64, 1>;
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@ -1038,8 +1015,6 @@ defm SQRDMULHvvv : NeonI_3VSame_HS_sizes<0b1, 0b10110, "sqrdmulh",
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// Vector Multiply Extended (Floating Point)
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defm FMULXvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11011, "fmulx",
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int_aarch64_neon_vmulx,
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int_aarch64_neon_vmulx,
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int_aarch64_neon_vmulx,
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v2f32, v4f32, v2f64, 1>;
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@ -5381,14 +5356,14 @@ defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_fcltz, SETLT,
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defm FACGE: NeonI_Scalar3Same_SD_sizes<0b1, 0b0, 0b11101, "facge">;
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defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_fcage, v1i32, f32,
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FACGEsss, v1i64, f64, FACGEddd>;
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def : Pat<(v1i64 (int_aarch64_neon_vcage (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
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def : Pat<(v1i64 (int_arm_neon_vacge (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
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(FACGEddd FPR64:$Rn, FPR64:$Rm)>;
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// Scalar Floating-point Absolute Compare Mask Greater Than
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defm FACGT: NeonI_Scalar3Same_SD_sizes<0b1, 0b1, 0b11101, "facgt">;
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defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_fcagt, v1i32, f32,
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FACGTsss, v1i64, f64, FACGTddd>;
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def : Pat<(v1i64 (int_aarch64_neon_vcagt (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
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def : Pat<(v1i64 (int_arm_neon_vacgt (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
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(FACGTddd FPR64:$Rn, FPR64:$Rm)>;
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// Scalar Floating-point Absolute Difference
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@ -4427,14 +4427,14 @@ defm VCLTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00100, 0, "vclt", "s",
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// VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
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def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacge",
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"f32", v2i32, v2f32, int_arm_neon_vacged, 0>;
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"f32", v2i32, v2f32, int_arm_neon_vacge, 0>;
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def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacge",
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"f32", v4i32, v4f32, int_arm_neon_vacgeq, 0>;
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"f32", v4i32, v4f32, int_arm_neon_vacge, 0>;
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// VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
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def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacgt",
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"f32", v2i32, v2f32, int_arm_neon_vacgtd, 0>;
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"f32", v2i32, v2f32, int_arm_neon_vacgt, 0>;
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def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacgt",
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"f32", v4i32, v4f32, int_arm_neon_vacgtq, 0>;
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"f32", v4i32, v4f32, int_arm_neon_vacgt, 0>;
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// VTST : Vector Test Bits
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defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
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IIC_VBINi4Q, "vtst", "", NEONvtst, 1>;
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@ -1,20 +1,20 @@
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; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
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declare <2 x i32> @llvm.arm.neon.vacged(<2 x float>, <2 x float>)
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declare <4 x i32> @llvm.arm.neon.vacgeq(<4 x float>, <4 x float>)
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declare <2 x i64> @llvm.aarch64.neon.vacgeq(<2 x double>, <2 x double>)
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declare <2 x i32> @llvm.arm.neon.vacge.v2i32.v2f32(<2 x float>, <2 x float>)
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declare <4 x i32> @llvm.arm.neon.vacge.v4i32.v4f32(<4 x float>, <4 x float>)
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declare <2 x i64> @llvm.arm.neon.vacge.v2i64.v2f64(<2 x double>, <2 x double>)
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define <2 x i32> @facge_from_intr_v2i32(<2 x float> %A, <2 x float> %B, <2 x float> %C) {
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; Using registers other than v0, v1 and v2 are possible, but would be odd.
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; CHECK: facge_from_intr_v2i32:
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%val = call <2 x i32> @llvm.arm.neon.vacged(<2 x float> %A, <2 x float> %B)
|
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%val = call <2 x i32> @llvm.arm.neon.vacge.v2i32.v2f32(<2 x float> %A, <2 x float> %B)
|
||||
; CHECK: facge {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
|
||||
ret <2 x i32> %val
|
||||
}
|
||||
define <4 x i32> @facge_from_intr_v4i32( <4 x float> %A, <4 x float> %B) {
|
||||
; Using registers other than v0, v1 and v2 are possible, but would be odd.
|
||||
; CHECK: facge_from_intr_v4i32:
|
||||
%val = call <4 x i32> @llvm.arm.neon.vacgeq(<4 x float> %A, <4 x float> %B)
|
||||
%val = call <4 x i32> @llvm.arm.neon.vacge.v4i32.v4f32(<4 x float> %A, <4 x float> %B)
|
||||
; CHECK: facge {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
|
||||
ret <4 x i32> %val
|
||||
}
|
||||
@ -22,26 +22,26 @@ define <4 x i32> @facge_from_intr_v4i32( <4 x float> %A, <4 x float> %B) {
|
||||
define <2 x i64> @facge_from_intr_v2i64(<2 x double> %A, <2 x double> %B) {
|
||||
; Using registers other than v0, v1 and v2 are possible, but would be odd.
|
||||
; CHECK: facge_from_intr_v2i64:
|
||||
%val = call <2 x i64> @llvm.aarch64.neon.vacgeq(<2 x double> %A, <2 x double> %B)
|
||||
%val = call <2 x i64> @llvm.arm.neon.vacge.v2i64.v2f64(<2 x double> %A, <2 x double> %B)
|
||||
; CHECK: facge {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
|
||||
ret <2 x i64> %val
|
||||
}
|
||||
|
||||
declare <2 x i32> @llvm.arm.neon.vacgtd(<2 x float>, <2 x float>)
|
||||
declare <4 x i32> @llvm.arm.neon.vacgtq(<4 x float>, <4 x float>)
|
||||
declare <2 x i64> @llvm.aarch64.neon.vacgtq(<2 x double>, <2 x double>)
|
||||
declare <2 x i32> @llvm.arm.neon.vacgt.v2i32.v2f32(<2 x float>, <2 x float>)
|
||||
declare <4 x i32> @llvm.arm.neon.vacgt.v4i32.v4f32(<4 x float>, <4 x float>)
|
||||
declare <2 x i64> @llvm.arm.neon.vacgt.v2i64.v2f64(<2 x double>, <2 x double>)
|
||||
|
||||
define <2 x i32> @facgt_from_intr_v2i32(<2 x float> %A, <2 x float> %B, <2 x float> %C) {
|
||||
; Using registers other than v0, v1 and v2 are possible, but would be odd.
|
||||
; CHECK: facgt_from_intr_v2i32:
|
||||
%val = call <2 x i32> @llvm.arm.neon.vacgtd(<2 x float> %A, <2 x float> %B)
|
||||
%val = call <2 x i32> @llvm.arm.neon.vacgt.v2i32.v2f32(<2 x float> %A, <2 x float> %B)
|
||||
; CHECK: facgt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
|
||||
ret <2 x i32> %val
|
||||
}
|
||||
define <4 x i32> @facgt_from_intr_v4i32( <4 x float> %A, <4 x float> %B) {
|
||||
; Using registers other than v0, v1 and v2 are possible, but would be odd.
|
||||
; CHECK: facgt_from_intr_v4i32:
|
||||
%val = call <4 x i32> @llvm.arm.neon.vacgtq(<4 x float> %A, <4 x float> %B)
|
||||
%val = call <4 x i32> @llvm.arm.neon.vacgt.v4i32.v4f32(<4 x float> %A, <4 x float> %B)
|
||||
; CHECK: facgt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
|
||||
ret <4 x i32> %val
|
||||
}
|
||||
@ -49,7 +49,7 @@ define <4 x i32> @facgt_from_intr_v4i32( <4 x float> %A, <4 x float> %B) {
|
||||
define <2 x i64> @facgt_from_intr_v2i64(<2 x double> %A, <2 x double> %B) {
|
||||
; Using registers other than v0, v1 and v2 are possible, but would be odd.
|
||||
; CHECK: facgt_from_intr_v2i64:
|
||||
%val = call <2 x i64> @llvm.aarch64.neon.vacgtq(<2 x double> %A, <2 x double> %B)
|
||||
%val = call <2 x i64> @llvm.arm.neon.vacgt.v2i64.v2f64(<2 x double> %A, <2 x double> %B)
|
||||
; CHECK: facgt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
|
||||
ret <2 x i64> %val
|
||||
}
|
||||
|
||||
@ -122,28 +122,28 @@ entry:
|
||||
define <1 x i64> @test_vcage_f64(<1 x double> %a, <1 x double> %b) #0 {
|
||||
; CHECK: test_vcage_f64
|
||||
; CHECK: facge {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
|
||||
%vcage2.i = tail call <1 x i64> @llvm.aarch64.neon.vcage.v1i64.v1f64.v1f64(<1 x double> %a, <1 x double> %b) #2
|
||||
%vcage2.i = tail call <1 x i64> @llvm.arm.neon.vacge.v1i64.v1f64(<1 x double> %a, <1 x double> %b) #2
|
||||
ret <1 x i64> %vcage2.i
|
||||
}
|
||||
|
||||
define <1 x i64> @test_vcagt_f64(<1 x double> %a, <1 x double> %b) #0 {
|
||||
; CHECK: test_vcagt_f64
|
||||
; CHECK: facgt {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
|
||||
%vcagt2.i = tail call <1 x i64> @llvm.aarch64.neon.vcagt.v1i64.v1f64.v1f64(<1 x double> %a, <1 x double> %b) #2
|
||||
%vcagt2.i = tail call <1 x i64> @llvm.arm.neon.vacgt.v1i64.v1f64(<1 x double> %a, <1 x double> %b) #2
|
||||
ret <1 x i64> %vcagt2.i
|
||||
}
|
||||
|
||||
define <1 x i64> @test_vcale_f64(<1 x double> %a, <1 x double> %b) #0 {
|
||||
; CHECK: test_vcale_f64
|
||||
; CHECK: facge {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
|
||||
%vcage2.i = tail call <1 x i64> @llvm.aarch64.neon.vcage.v1i64.v1f64.v1f64(<1 x double> %b, <1 x double> %a) #2
|
||||
%vcage2.i = tail call <1 x i64> @llvm.arm.neon.vacge.v1i64.v1f64(<1 x double> %b, <1 x double> %a) #2
|
||||
ret <1 x i64> %vcage2.i
|
||||
}
|
||||
|
||||
define <1 x i64> @test_vcalt_f64(<1 x double> %a, <1 x double> %b) #0 {
|
||||
; CHECK: test_vcalt_f64
|
||||
; CHECK: facgt {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
|
||||
%vcagt2.i = tail call <1 x i64> @llvm.aarch64.neon.vcagt.v1i64.v1f64.v1f64(<1 x double> %b, <1 x double> %a) #2
|
||||
%vcagt2.i = tail call <1 x i64> @llvm.arm.neon.vacgt.v1i64.v1f64(<1 x double> %b, <1 x double> %a) #2
|
||||
ret <1 x i64> %vcagt2.i
|
||||
}
|
||||
|
||||
@ -331,8 +331,8 @@ define <1 x i64> @test_vcltz_s64(<1 x i64> %a) #0 {
|
||||
ret <1 x i64> %vcltz.i
|
||||
}
|
||||
|
||||
declare <1 x i64> @llvm.aarch64.neon.vcagt.v1i64.v1f64.v1f64(<1 x double>, <1 x double>)
|
||||
declare <1 x i64> @llvm.aarch64.neon.vcage.v1i64.v1f64.v1f64(<1 x double>, <1 x double>)
|
||||
declare <1 x i64> @llvm.arm.neon.vacgt.v1i64.v1f64(<1 x double>, <1 x double>)
|
||||
declare <1 x i64> @llvm.arm.neon.vacge.v1i64.v1f64(<1 x double>, <1 x double>)
|
||||
declare <1 x i64> @llvm.aarch64.neon.vtstd.v1i64.v1i64.v1i64(<1 x i64>, <1 x i64>)
|
||||
declare <1 x i64> @llvm.aarch64.neon.vcltz.v1i64.v1i64.v1i64(<1 x i64>, <1 x i64>)
|
||||
declare <1 x i64> @llvm.aarch64.neon.vchs.v1i64.v1i64.v1i64(<1 x i64>, <1 x i64>)
|
||||
|
||||
@ -145,7 +145,7 @@ define <2 x i32> @vacgef32(<2 x float>* %A, <2 x float>* %B) nounwind {
|
||||
;CHECK: vacge.f32
|
||||
%tmp1 = load <2 x float>* %A
|
||||
%tmp2 = load <2 x float>* %B
|
||||
%tmp3 = call <2 x i32> @llvm.arm.neon.vacged(<2 x float> %tmp1, <2 x float> %tmp2)
|
||||
%tmp3 = call <2 x i32> @llvm.arm.neon.vacge.v2i32.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
|
||||
ret <2 x i32> %tmp3
|
||||
}
|
||||
|
||||
@ -154,12 +154,12 @@ define <4 x i32> @vacgeQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
|
||||
;CHECK: vacge.f32
|
||||
%tmp1 = load <4 x float>* %A
|
||||
%tmp2 = load <4 x float>* %B
|
||||
%tmp3 = call <4 x i32> @llvm.arm.neon.vacgeq(<4 x float> %tmp1, <4 x float> %tmp2)
|
||||
%tmp3 = call <4 x i32> @llvm.arm.neon.vacge.v4i32.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
|
||||
ret <4 x i32> %tmp3
|
||||
}
|
||||
|
||||
declare <2 x i32> @llvm.arm.neon.vacged(<2 x float>, <2 x float>) nounwind readnone
|
||||
declare <4 x i32> @llvm.arm.neon.vacgeq(<4 x float>, <4 x float>) nounwind readnone
|
||||
declare <2 x i32> @llvm.arm.neon.vacge.v2i32.v2f32(<2 x float>, <2 x float>) nounwind readnone
|
||||
declare <4 x i32> @llvm.arm.neon.vacge.v4i32.v4f32(<4 x float>, <4 x float>) nounwind readnone
|
||||
|
||||
define <8 x i8> @vcgei8Z(<8 x i8>* %A) nounwind {
|
||||
;CHECK-LABEL: vcgei8Z:
|
||||
|
||||
@ -146,7 +146,7 @@ define <2 x i32> @vacgtf32(<2 x float>* %A, <2 x float>* %B) nounwind {
|
||||
;CHECK: vacgt.f32
|
||||
%tmp1 = load <2 x float>* %A
|
||||
%tmp2 = load <2 x float>* %B
|
||||
%tmp3 = call <2 x i32> @llvm.arm.neon.vacgtd(<2 x float> %tmp1, <2 x float> %tmp2)
|
||||
%tmp3 = call <2 x i32> @llvm.arm.neon.vacgt.v2i32.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
|
||||
ret <2 x i32> %tmp3
|
||||
}
|
||||
|
||||
@ -155,7 +155,7 @@ define <4 x i32> @vacgtQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
|
||||
;CHECK: vacgt.f32
|
||||
%tmp1 = load <4 x float>* %A
|
||||
%tmp2 = load <4 x float>* %B
|
||||
%tmp3 = call <4 x i32> @llvm.arm.neon.vacgtq(<4 x float> %tmp1, <4 x float> %tmp2)
|
||||
%tmp3 = call <4 x i32> @llvm.arm.neon.vacgt.v4i32.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
|
||||
ret <4 x i32> %tmp3
|
||||
}
|
||||
|
||||
@ -172,8 +172,8 @@ define <4 x i32> @vcgt_zext(<4 x float>* %A, <4 x float>* %B) nounwind {
|
||||
ret <4 x i32> %tmp4
|
||||
}
|
||||
|
||||
declare <2 x i32> @llvm.arm.neon.vacgtd(<2 x float>, <2 x float>) nounwind readnone
|
||||
declare <4 x i32> @llvm.arm.neon.vacgtq(<4 x float>, <4 x float>) nounwind readnone
|
||||
declare <2 x i32> @llvm.arm.neon.vacgt.v2i32.v2f32(<2 x float>, <2 x float>) nounwind readnone
|
||||
declare <4 x i32> @llvm.arm.neon.vacgt.v4i32.v4f32(<4 x float>, <4 x float>) nounwind readnone
|
||||
|
||||
define <8 x i8> @vcgti8Z(<8 x i8>* %A) nounwind {
|
||||
;CHECK-LABEL: vcgti8Z:
|
||||
|
||||
Loading…
Reference in New Issue
Block a user