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[mips] [IAS] Rename the createShiftOr function to createLShiftOri. NFC.
Summary: The new name is more accurate with regard to the functionality. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8968 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235984 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1633,7 +1633,7 @@ bool MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
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namespace {
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namespace {
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template <bool PerformShift>
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template <bool PerformShift>
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void createShiftOr(MCOperand Operand, unsigned RegNo, SMLoc IDLoc,
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void createLShiftOri(MCOperand Operand, unsigned RegNo, SMLoc IDLoc,
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SmallVectorImpl<MCInst> &Instructions) {
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SmallVectorImpl<MCInst> &Instructions) {
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MCInst tmpInst;
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MCInst tmpInst;
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if (PerformShift) {
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if (PerformShift) {
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@ -1654,9 +1654,9 @@ void createShiftOr(MCOperand Operand, unsigned RegNo, SMLoc IDLoc,
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}
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}
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template <int Shift, bool PerformShift>
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template <int Shift, bool PerformShift>
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void createShiftOr(int64_t Value, unsigned RegNo, SMLoc IDLoc,
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void createLShiftOri(int64_t Value, unsigned RegNo, SMLoc IDLoc,
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SmallVectorImpl<MCInst> &Instructions) {
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SmallVectorImpl<MCInst> &Instructions) {
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createShiftOr<PerformShift>(
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createLShiftOri<PerformShift>(
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MCOperand::CreateImm(((Value & (0xffffLL << Shift)) >> Shift)), RegNo,
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MCOperand::CreateImm(((Value & (0xffffLL << Shift)) >> Shift)), RegNo,
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IDLoc, Instructions);
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IDLoc, Instructions);
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}
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}
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@ -1741,7 +1741,7 @@ bool MipsAsmParser::expandLoadImm(MCInst &Inst, SMLoc IDLoc,
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tmpInst.addOperand(MCOperand::CreateReg(Reg));
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tmpInst.addOperand(MCOperand::CreateReg(Reg));
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tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
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tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
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Instructions.push_back(tmpInst);
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Instructions.push_back(tmpInst);
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createShiftOr<0, false>(ImmValue, Reg, IDLoc, Instructions);
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createLShiftOri<0, false>(ImmValue, Reg, IDLoc, Instructions);
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} else if ((ImmValue & (0xffffLL << 48)) == 0) {
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} else if ((ImmValue & (0xffffLL << 48)) == 0) {
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if (!isGP64bit()) {
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if (!isGP64bit()) {
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Error(IDLoc, "instruction requires a 64-bit architecture");
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Error(IDLoc, "instruction requires a 64-bit architecture");
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@ -1766,8 +1766,8 @@ bool MipsAsmParser::expandLoadImm(MCInst &Inst, SMLoc IDLoc,
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tmpInst.addOperand(
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tmpInst.addOperand(
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MCOperand::CreateImm((ImmValue & (0xffffLL << 32)) >> 32));
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MCOperand::CreateImm((ImmValue & (0xffffLL << 32)) >> 32));
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Instructions.push_back(tmpInst);
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Instructions.push_back(tmpInst);
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createShiftOr<16, false>(ImmValue, Reg, IDLoc, Instructions);
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createLShiftOri<16, false>(ImmValue, Reg, IDLoc, Instructions);
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createShiftOr<0, true>(ImmValue, Reg, IDLoc, Instructions);
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createLShiftOri<0, true>(ImmValue, Reg, IDLoc, Instructions);
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} else {
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} else {
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if (!isGP64bit()) {
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if (!isGP64bit()) {
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Error(IDLoc, "instruction requires a 64-bit architecture");
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Error(IDLoc, "instruction requires a 64-bit architecture");
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@ -1793,9 +1793,9 @@ bool MipsAsmParser::expandLoadImm(MCInst &Inst, SMLoc IDLoc,
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tmpInst.addOperand(
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tmpInst.addOperand(
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MCOperand::CreateImm((ImmValue & (0xffffLL << 48)) >> 48));
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MCOperand::CreateImm((ImmValue & (0xffffLL << 48)) >> 48));
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Instructions.push_back(tmpInst);
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Instructions.push_back(tmpInst);
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createShiftOr<32, false>(ImmValue, Reg, IDLoc, Instructions);
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createLShiftOri<32, false>(ImmValue, Reg, IDLoc, Instructions);
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createShiftOr<16, true>(ImmValue, Reg, IDLoc, Instructions);
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createLShiftOri<16, true>(ImmValue, Reg, IDLoc, Instructions);
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createShiftOr<0, true>(ImmValue, Reg, IDLoc, Instructions);
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createLShiftOri<0, true>(ImmValue, Reg, IDLoc, Instructions);
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}
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}
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return false;
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return false;
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}
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}
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@ -1934,11 +1934,11 @@ MipsAsmParser::expandLoadAddressSym(MCInst &Inst, SMLoc IDLoc,
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tmpInst.addOperand(MCOperand::CreateExpr(HighestExpr));
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tmpInst.addOperand(MCOperand::CreateExpr(HighestExpr));
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Instructions.push_back(tmpInst);
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Instructions.push_back(tmpInst);
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createShiftOr<false>(MCOperand::CreateExpr(HigherExpr), RegNo, SMLoc(),
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createLShiftOri<false>(MCOperand::CreateExpr(HigherExpr), RegNo, SMLoc(),
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Instructions);
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Instructions);
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createShiftOr<true>(MCOperand::CreateExpr(HiExpr), RegNo, SMLoc(),
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createLShiftOri<true>(MCOperand::CreateExpr(HiExpr), RegNo, SMLoc(),
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Instructions);
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Instructions);
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createShiftOr<true>(MCOperand::CreateExpr(LoExpr), RegNo, SMLoc(),
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createLShiftOri<true>(MCOperand::CreateExpr(LoExpr), RegNo, SMLoc(),
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Instructions);
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Instructions);
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} else {
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} else {
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// Otherwise, expand to:
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// Otherwise, expand to:
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@ -1949,7 +1949,7 @@ MipsAsmParser::expandLoadAddressSym(MCInst &Inst, SMLoc IDLoc,
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tmpInst.addOperand(MCOperand::CreateExpr(HiExpr));
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tmpInst.addOperand(MCOperand::CreateExpr(HiExpr));
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Instructions.push_back(tmpInst);
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Instructions.push_back(tmpInst);
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createShiftOr<false>(MCOperand::CreateExpr(LoExpr), RegNo, SMLoc(),
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createLShiftOri<false>(MCOperand::CreateExpr(LoExpr), RegNo, SMLoc(),
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Instructions);
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Instructions);
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}
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}
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}
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}
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