mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-17 21:29:20 +00:00
This seems useful from the original patch that added the function. If there is a reason it is not useful on a RISC type target, let me know and I will pull it out
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23676 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
60de63d0b6
commit
fa08fb2c78
@ -107,6 +107,25 @@ AlphaRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
|
||||
abort();
|
||||
}
|
||||
|
||||
unsigned
|
||||
AlphaRegisterInfo::isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const
|
||||
{
|
||||
switch (MI->getOpcode()) {
|
||||
case Alpha::LDL:
|
||||
case Alpha::LDQ:
|
||||
case Alpha::LDBU:
|
||||
case Alpha::LDWU:
|
||||
case Alpha::LDS:
|
||||
case Alpha::LDT:
|
||||
if (MI->getOperand(1).isFrameIndex()) {
|
||||
FrameIndex = MI->getOperand(1).getFrameIndex();
|
||||
return MI->getOperand(0).getReg();
|
||||
}
|
||||
break;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
void AlphaRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator MI,
|
||||
unsigned DestReg, unsigned SrcReg,
|
||||
|
@ -34,6 +34,8 @@ struct AlphaRegisterInfo : public AlphaGenRegisterInfo {
|
||||
MachineBasicBlock::iterator MBBI,
|
||||
unsigned DestReg, int FrameIndex,
|
||||
const TargetRegisterClass *RC) const;
|
||||
|
||||
virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
|
||||
|
||||
void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
|
||||
unsigned DestReg, unsigned SrcReg,
|
||||
|
Loading…
Reference in New Issue
Block a user