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Fix PR4687. Pre ARMv5te does not support ldrd / strd. Patch by John Tytgat.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83058 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2009-09-29 07:07:30 +00:00
parent 4372e69770
commit fa1be5d991
2 changed files with 23 additions and 0 deletions
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4
lib/Target/ARM/ARMLoadStoreOptimizer.cpp
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@ -1191,6 +1191,10 @@ ARMPreAllocLoadStoreOpt::CanFormLdStDWord(MachineInstr *Op0, MachineInstr *Op1,
unsigned &PredReg,
ARMCC::CondCodes &Pred,
bool &isT2) {
// Make sure we're allowed to generate LDRD/STRD.
if (!STI->hasV5TEOps())
return false;
// FIXME: FLDS / FSTS -> FLDD / FSTD
unsigned Scale = 1;
unsigned Opcode = Op0->getOpcode();

19
test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll Normal file
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@ -0,0 +1,19 @@
; RUN: llc < %s -mtriple=armv5-unknown-linux-gnueabi -mcpu=arm10tdmi | FileCheck %s
; PR4687
%0 = type { double, double }
define arm_aapcscc void @foo(%0* noalias nocapture sret %agg.result, double %x.0, double %y.0) nounwind {
; CHECK: foo:
; CHECK: bl __adddf3
; CHECK-NOT: strd
; CHECK: mov
%x76 = fmul double %y.0, 0.000000e+00 ; <double> [#uses=1]
%x77 = fadd double %y.0, 0.000000e+00 ; <double> [#uses=1]
%tmpr = fadd double %x.0, %x76 ; <double> [#uses=1]
%agg.result.0 = getelementptr %0* %agg.result, i32 0, i32 0 ; <double*> [#uses=1]
store double %tmpr, double* %agg.result.0, align 8
%agg.result.1 = getelementptr %0* %agg.result, i32 0, i32 1 ; <double*> [#uses=1]
store double %x77, double* %agg.result.1, align 8
ret void
}