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Added support for unpredictable mcrr/mcrr2/mrrc/mrrc2 ARM instruction in the disassembler. Since the upredicability conditions are complex, C++ code was added to handle them.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155001 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Silviu Baranga
2012-04-18 13:12:50 +00:00
parent e546c4c9c3
commit fa1ebc6abe
4 changed files with 53 additions and 4 deletions
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lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+30
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@@ -326,6 +326,8 @@ static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder);
#include "ARMGenDisassemblerTables.inc"
#include "ARMGenInstrInfo.inc"
#include "ARMGenEDInfo.inc"
@@ -4403,3 +4405,31 @@ static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
return S;
}
static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success;
unsigned CRm = fieldFromInstruction32(Val, 0, 4);
unsigned opc1 = fieldFromInstruction32(Val, 4, 4);
unsigned cop = fieldFromInstruction32(Val, 8, 4);
unsigned Rt = fieldFromInstruction32(Val, 12, 4);
unsigned Rt2 = fieldFromInstruction32(Val, 16, 4);
if ((cop & ~0x1) == 0xa)
return MCDisassembler::Fail;
if (Rt == Rt2)
S = MCDisassembler::SoftFail;
Inst.addOperand(MCOperand::CreateImm(cop));
Inst.addOperand(MCOperand::CreateImm(opc1));
if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
return MCDisassembler::Fail;
if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(CRm));
return S;
}