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Build COND_BRANCHes which may become long or short, decided by a later pass.

Browse Source 
Patch by Nate Begeman.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15282 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Misha Brukman 2004-07-27 18:35:23 +00:00
parent 8aebe9f96c
commit fa20a6dfd7
2 changed files with 28 additions and 46 deletions
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37
lib/Target/PowerPC/PPC32ISelSimple.cpp
View File

@ -944,18 +944,6 @@ static unsigned getPPCOpcodeForSetCCNumber(unsigned Opcode) {
}
}
static unsigned invertPPCBranchOpcode(unsigned Opcode) {
switch (Opcode) {
default: assert(0 && "Unknown PPC32 branch opcode!");
case PPC32::BEQ: return PPC32::BNE;
case PPC32::BNE: return PPC32::BEQ;
case PPC32::BLT: return PPC32::BGE;
case PPC32::BGE: return PPC32::BLT;
case PPC32::BGT: return PPC32::BLE;
case PPC32::BLE: return PPC32::BGT;
}
}
/// emitUCOM - emits an unordered FP compare.
void ISel::emitUCOM(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
unsigned LHS, unsigned RHS) {
@ -1369,16 +1357,17 @@ void ISel::visitBranchInst(BranchInst &BI) {
// Nope, cannot fold setcc into this branch. Emit a branch on a condition
// computed some other way...
unsigned condReg = getReg(BI.getCondition());
BuildMI(BB, PPC32::CMPLI, 3, PPC32::CR1).addImm(0).addReg(condReg)
BuildMI(BB, PPC32::CMPLI, 3, PPC32::CR0).addImm(0).addReg(condReg)
.addImm(0);
if (BI.getSuccessor(1) == NextBB) {
if (BI.getSuccessor(0) != NextBB)
BuildMI(BB, PPC32::BNE, 2).addReg(PPC32::CR1)
.addMBB(MBBMap[BI.getSuccessor(0)]);
BuildMI(BB, PPC32::COND_BRANCH, 3).addReg(PPC32::CR0).addImm(PPC32::BNE)
.addMBB(MBBMap[BI.getSuccessor(0)])
.addMBB(MBBMap[BI.getSuccessor(1)]);
} else {
BuildMI(BB, PPC32::BEQ, 2).addReg(PPC32::CR1)
.addMBB(MBBMap[BI.getSuccessor(1)]);
BuildMI(BB, PPC32::COND_BRANCH, 3).addReg(PPC32::CR0).addImm(PPC32::BEQ)
.addMBB(MBBMap[BI.getSuccessor(1)])
.addMBB(MBBMap[BI.getSuccessor(0)]);
if (BI.getSuccessor(0) != NextBB)
BuildMI(BB, PPC32::B, 1).addMBB(MBBMap[BI.getSuccessor(0)]);
}
@ -1391,16 +1380,18 @@ void ISel::visitBranchInst(BranchInst &BI) {
OpNum = EmitComparison(OpNum, SCI->getOperand(0), SCI->getOperand(1), BB,MII);
if (BI.getSuccessor(0) != NextBB) {
BuildMI(BB, Opcode, 2).addReg(PPC32::CR0)
.addMBB(MBBMap[BI.getSuccessor(0)]);
BuildMI(BB, PPC32::COND_BRANCH, 3).addReg(PPC32::CR0).addImm(Opcode)
.addMBB(MBBMap[BI.getSuccessor(0)])
.addMBB(MBBMap[BI.getSuccessor(1)]);
if (BI.getSuccessor(1) != NextBB)
BuildMI(BB, PPC32::B, 1).addMBB(MBBMap[BI.getSuccessor(1)]);
} else {
// Change to the inverse condition...
if (BI.getSuccessor(1) != NextBB) {
Opcode = invertPPCBranchOpcode(Opcode);
BuildMI(BB, Opcode, 2).addReg(PPC32::CR0)
.addMBB(MBBMap[BI.getSuccessor(1)]);
Opcode = PowerPCInstrInfo::invertPPCBranchOpcode(Opcode);
BuildMI(BB, PPC32::COND_BRANCH, 3).addReg(PPC32::CR0).addImm(Opcode)
.addMBB(MBBMap[BI.getSuccessor(1)])
.addMBB(MBBMap[BI.getSuccessor(0)]);
}
}
}

37
lib/Target/PowerPC/PowerPCISelSimple.cpp
View File

@ -944,18 +944,6 @@ static unsigned getPPCOpcodeForSetCCNumber(unsigned Opcode) {
}
}
static unsigned invertPPCBranchOpcode(unsigned Opcode) {
switch (Opcode) {
default: assert(0 && "Unknown PPC32 branch opcode!");
case PPC32::BEQ: return PPC32::BNE;
case PPC32::BNE: return PPC32::BEQ;
case PPC32::BLT: return PPC32::BGE;
case PPC32::BGE: return PPC32::BLT;
case PPC32::BGT: return PPC32::BLE;
case PPC32::BLE: return PPC32::BGT;
}
}
/// emitUCOM - emits an unordered FP compare.
void ISel::emitUCOM(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
unsigned LHS, unsigned RHS) {
@ -1369,16 +1357,17 @@ void ISel::visitBranchInst(BranchInst &BI) {
// Nope, cannot fold setcc into this branch. Emit a branch on a condition
// computed some other way...
unsigned condReg = getReg(BI.getCondition());
BuildMI(BB, PPC32::CMPLI, 3, PPC32::CR1).addImm(0).addReg(condReg)
BuildMI(BB, PPC32::CMPLI, 3, PPC32::CR0).addImm(0).addReg(condReg)
.addImm(0);
if (BI.getSuccessor(1) == NextBB) {
if (BI.getSuccessor(0) != NextBB)
BuildMI(BB, PPC32::BNE, 2).addReg(PPC32::CR1)
.addMBB(MBBMap[BI.getSuccessor(0)]);
BuildMI(BB, PPC32::COND_BRANCH, 3).addReg(PPC32::CR0).addImm(PPC32::BNE)
.addMBB(MBBMap[BI.getSuccessor(0)])
.addMBB(MBBMap[BI.getSuccessor(1)]);
} else {
BuildMI(BB, PPC32::BEQ, 2).addReg(PPC32::CR1)
.addMBB(MBBMap[BI.getSuccessor(1)]);
BuildMI(BB, PPC32::COND_BRANCH, 3).addReg(PPC32::CR0).addImm(PPC32::BEQ)
.addMBB(MBBMap[BI.getSuccessor(1)])
.addMBB(MBBMap[BI.getSuccessor(0)]);
if (BI.getSuccessor(0) != NextBB)
BuildMI(BB, PPC32::B, 1).addMBB(MBBMap[BI.getSuccessor(0)]);
}
@ -1391,16 +1380,18 @@ void ISel::visitBranchInst(BranchInst &BI) {
OpNum = EmitComparison(OpNum, SCI->getOperand(0), SCI->getOperand(1), BB,MII);
if (BI.getSuccessor(0) != NextBB) {
BuildMI(BB, Opcode, 2).addReg(PPC32::CR0)
.addMBB(MBBMap[BI.getSuccessor(0)]);
BuildMI(BB, PPC32::COND_BRANCH, 3).addReg(PPC32::CR0).addImm(Opcode)
.addMBB(MBBMap[BI.getSuccessor(0)])
.addMBB(MBBMap[BI.getSuccessor(1)]);
if (BI.getSuccessor(1) != NextBB)
BuildMI(BB, PPC32::B, 1).addMBB(MBBMap[BI.getSuccessor(1)]);
} else {
// Change to the inverse condition...
if (BI.getSuccessor(1) != NextBB) {
Opcode = invertPPCBranchOpcode(Opcode);
BuildMI(BB, Opcode, 2).addReg(PPC32::CR0)
.addMBB(MBBMap[BI.getSuccessor(1)]);
Opcode = PowerPCInstrInfo::invertPPCBranchOpcode(Opcode);
BuildMI(BB, PPC32::COND_BRANCH, 3).addReg(PPC32::CR0).addImm(Opcode)
.addMBB(MBBMap[BI.getSuccessor(1)])
.addMBB(MBBMap[BI.getSuccessor(0)]);
}
}
}