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Use TRI::has{Sub,Super}ClassEq() where possible.

Browse Source 
No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132455 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2011-06-02 05:43:46 +00:00
parent ac92565384
commit fa226bccaa
7 changed files with 8 additions and 10 deletions
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2
lib/CodeGen/MachineVerifier.cpp
View File

@ -744,7 +744,7 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
RC = SRC;
}
if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) {
if (RC != DRC && !RC->hasSuperClass(DRC)) {
if (!RC->hasSuperClassEq(DRC)) {
report("Illegal virtual register for instruction", MO, MONum);
*OS << "Expected a " << DRC->getName() << " register, but got a "
<< RC->getName() << " register\n";

2
lib/CodeGen/SelectionDAG/InstrEmitter.cpp
View File

@ -283,7 +283,7 @@ InstrEmitter::AddRegisterOperand(MachineInstr *MI, SDValue Op,
DstRC = II->OpInfo[IIOpNum].getRegClass(TRI);
assert((DstRC || (TID.isVariadic() && IIOpNum >= TID.getNumOperands())) &&
"Don't have operand info for this instruction!");
if (DstRC && SrcRC != DstRC && !SrcRC->hasSuperClass(DstRC)) {
if (DstRC && !SrcRC->hasSuperClassEq(DstRC)) {
unsigned NewVReg = MRI->createVirtualRegister(DstRC);
BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);

3
lib/CodeGen/TargetInstrInfoImpl.cpp
View File

@ -212,8 +212,7 @@ static const TargetRegisterClass *canFoldCopy(const MachineInstr *MI,
if (TargetRegisterInfo::isPhysicalRegister(LiveOp.getReg()))
return RC->contains(LiveOp.getReg()) ? RC : 0;
const TargetRegisterClass *LiveRC = MRI.getRegClass(LiveReg);
if (RC == LiveRC || RC->hasSubClass(LiveRC))
if (RC->hasSubClassEq(MRI.getRegClass(LiveReg)))
return RC;
// FIXME: Allow folding when register classes are memory compatible.

2
lib/Target/ARM/Thumb1RegisterInfo.cpp
View File

@ -49,7 +49,7 @@ Thumb1RegisterInfo::Thumb1RegisterInfo(const ARMBaseInstrInfo &tii,
const TargetRegisterClass*
Thumb1RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC)
const {
if (RC == ARM::tGPRRegisterClass || RC->hasSuperClass(ARM::tGPRRegisterClass))
if (ARM::tGPRRegClass.hasSubClassEq(RC))
return ARM::tGPRRegisterClass;
return ARMBaseRegisterInfo::getLargestLegalSuperClass(RC);
}

4
lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp
View File

@ -117,11 +117,11 @@ bool BlackfinDAGToDAGISel::SelectADDRspii(SDValue Addr,
}
static inline bool isCC(const TargetRegisterClass *RC) {
return RC == &BF::AnyCCRegClass || BF::AnyCCRegClass.hasSubClass(RC);
return BF::AnyCCRegClass.hasSubClassEq(RC);
}
static inline bool isDCC(const TargetRegisterClass *RC) {
return RC == &BF::DRegClass || BF::DRegClass.hasSubClass(RC) || isCC(RC);
return BF::DRegClass.hasSubClassEq(RC) || isCC(RC);
}
static void UpdateNodeOperand(SelectionDAG &DAG,

2
lib/Target/Blackfin/BlackfinInstrInfo.cpp
View File

@ -160,7 +160,7 @@ static bool inClass(const TargetRegisterClass &Test,
if (TargetRegisterInfo::isPhysicalRegister(Reg))
return Test.contains(Reg);
else
return &Test==RC || Test.hasSubClass(RC);
return Test.hasSubClassEq(RC);
}
void

3
lib/Target/X86/X86RegisterInfo.cpp
View File

@ -261,8 +261,7 @@ X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
}
break;
case X86::sub_8bit_hi:
if (B == &X86::GR8_ABCD_HRegClass ||
B->hasSubClass(&X86::GR8_ABCD_HRegClass))
if (B->hasSubClassEq(&X86::GR8_ABCD_HRegClass))
switch (A->getSize()) {
case 2: return getCommonSubClass(A, &X86::GR16_ABCDRegClass);
case 4: return getCommonSubClass(A, &X86::GR32_ABCDRegClass);