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Emit sub r, #c instead of transforming it to add r, #-c if c fits in 8-bit. This is a bit of pre-mature optimization. 8-bit variant makes it likely it will be narrowed to a 16-bit instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78030 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -83,6 +83,10 @@ def imm0_4095_neg : PatLeaf<(i32 imm), [{
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return (uint32_t)(-N->getZExtValue()) < 4096;
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}], imm_neg_XFORM>;
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def imm0_255_neg : PatLeaf<(i32 imm), [{
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return (uint32_t)(-N->getZExtValue()) < 255;
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}], imm_neg_XFORM>;
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/// imm0_65535 predicate - True if the 32-bit immediate is in the range
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/// [0.65535].
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def imm0_65535 : PatLeaf<(i32 imm), [{
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@ -619,12 +623,12 @@ def t2STRB_POST : T2Iidxldst<(outs GPR:$base_wb),
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let mayLoad = 1 in
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def t2LDM : T2XI<(outs),
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(ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
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"ldm${addr:submode}${p}.w $addr, $dst1", []>;
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"ldm${addr:submode}${p} $addr, $dst1", []>;
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let mayStore = 1 in
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def t2STM : T2XI<(outs),
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(ins addrmode4:$addr, pred:$p, reglist:$src1, variable_ops),
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"stm${addr:submode}${p}.w $addr, $src1", []>;
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"stm${addr:submode}${p} $addr, $src1", []>;
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//===----------------------------------------------------------------------===//
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// Move Instructions.
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@ -704,6 +708,9 @@ defm t2RSB : T2I_rbin_is <"rsb", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
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defm t2RSBS : T2I_rbin_s_is <"rsb", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
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// (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
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let AddedComplexity = 1 in
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def : T2Pat<(add GPR:$src, imm0_255_neg:$imm),
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(t2SUBri GPR:$src, imm0_255_neg:$imm)>;
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def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
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(t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
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def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
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@ -1,31 +1,49 @@
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; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {sub\\.w\\W*r\[0-9\],\\W*r\[0-9\],\\W*#\[0-9\]*} | grep {#171\\|#1179666\\|#872428544\\|#1448498774\\|#510} | count 5
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; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | FileCheck %s
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; 171 = 0x000000ab
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define i32 @f1(i32 %a) {
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; CHECK: f1:
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; CHECK: sub.w r0, r0, #171
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%tmp = sub i32 %a, 171
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ret i32 %tmp
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}
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; 1179666 = 0x00120012
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define i32 @f2(i32 %a) {
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; CHECK: f2:
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; CHECK: sub.w r0, r0, #1179666
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%tmp = sub i32 %a, 1179666
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ret i32 %tmp
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}
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; 872428544 = 0x34003400
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define i32 @f3(i32 %a) {
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; CHECK: f3:
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; CHECK: sub.w r0, r0, #872428544
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%tmp = sub i32 %a, 872428544
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ret i32 %tmp
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}
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; 1448498774 = 0x56565656
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define i32 @f4(i32 %a) {
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; CHECK: f4:
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; CHECK: sub.w r0, r0, #1448498774
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%tmp = sub i32 %a, 1448498774
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ret i32 %tmp
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}
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; 510 = 0x000001fe
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define i32 @f5(i32 %a) {
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; CHECK: f5:
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; CHECK: sub.w r0, r0, #510
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%tmp = sub i32 %a, 510
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ret i32 %tmp
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}
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; Don't change this to an add.
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define i32 @f6(i32 %a) {
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; CHECK: f6:
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; CHECK: sub.w r0, r0, #1
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%tmp = sub i32 %a, 1
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ret i32 %tmp
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}
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