From fa49d1ade646780df1e65815813f6236dc18e678 Mon Sep 17 00:00:00 2001 From: Jim Grosbach Date: Mon, 21 Apr 2014 21:45:44 +0000 Subject: [PATCH] ARM64: Extended addressing mode source reg is 64-bit. The canonical form for the extended addressing mode (e.g., "[x1, w2, uxtw #3]" is for the MCInst to have the second register be the full 64-bit GPR64 register class. The instruction printer cleans up the output for display to show the 32-bit register instead, per the specification. This simplifies 205893 now that the aliasing is handled in the printer in 206495 so that the codegen path and the disassembler path give the same MCInst form. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206797 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp b/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp index ba696b48854..8a334e2f1b7 100644 --- a/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp +++ b/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp @@ -1182,11 +1182,7 @@ static DecodeStatus DecodeRegOffsetLdStInstruction(llvm::MCInst &Inst, } DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); - - if ((extendHi & 0x3) == 0x3) - DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); - else - DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); + DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); Inst.addOperand(MCOperand::CreateImm(extend)); return Success;