From fa49d7d6e4384381e4307a0d2495e6e5b15821e3 Mon Sep 17 00:00:00 2001 From: David Majnemer Date: Sun, 12 May 2013 00:07:05 +0000 Subject: [PATCH] InstCombine: Flip the order of two urem transforms There are two transforms in visitUrem that conflict with each other. *) One, if a divisor is a power of two, subtracts one from the divisor and turns it into a bitwise-and. *) The other unwraps both operands if they are surrounded by zext instructions. Flipping the order allows the subtraction to go beneath the sign extension. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181668 91177308-0d34-0410-b5e6-96231b3b80d8 --- .../InstCombine/InstCombineMulDivRem.cpp | 12 ++++++------ test/Transforms/InstCombine/rem.ll | 14 ++++++++++++++ 2 files changed, 20 insertions(+), 6 deletions(-) diff --git a/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp b/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp index 249407818fd..87d56214a36 100644 --- a/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp +++ b/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp @@ -1027,6 +1027,12 @@ Instruction *InstCombiner::visitURem(BinaryOperator &I) { if (Instruction *common = commonIRemTransforms(I)) return common; + // (zext A) urem (zext B) --> zext (A urem B) + if (ZExtInst *ZOp0 = dyn_cast(Op0)) + if (Value *ZOp1 = dyn_castZExtVal(Op1, ZOp0->getSrcTy())) + return new ZExtInst(Builder->CreateURem(ZOp0->getOperand(0), ZOp1), + I.getType()); + // X urem Y -> X and Y-1, where Y is a power of 2, if (isKnownToBeAPowerOfTwo(Op1, /*OrZero*/true)) { Constant *N1 = Constant::getAllOnesValue(I.getType()); @@ -1034,12 +1040,6 @@ Instruction *InstCombiner::visitURem(BinaryOperator &I) { return BinaryOperator::CreateAnd(Op0, Add); } - // (zext A) urem (zext B) --> zext (A urem B) - if (ZExtInst *ZOp0 = dyn_cast(Op0)) - if (Value *ZOp1 = dyn_castZExtVal(Op1, ZOp0->getSrcTy())) - return new ZExtInst(Builder->CreateURem(ZOp0->getOperand(0), ZOp1), - I.getType()); - return 0; } diff --git a/test/Transforms/InstCombine/rem.ll b/test/Transforms/InstCombine/rem.ll index 9b8b98a1708..450a62ae6de 100644 --- a/test/Transforms/InstCombine/rem.ll +++ b/test/Transforms/InstCombine/rem.ll @@ -135,3 +135,17 @@ define i64 @test14(i64 %x, i32 %y) { %urem = urem i64 %x, %zext ret i64 %urem } + +define i64 @test15(i32 %x, i32 %y) { +; CHECK: @test15 +; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 1, %y +; CHECK-NEXT: [[ADD:%.*]] = add i32 [[SHL]], -1 +; CHECK-NEXT: [[AND:%.*]] = and i32 [[ADD]], %x +; CHECK-NEXT: [[ZEXT:%.*]] = zext i32 [[AND]] to i64 +; CHECK-NEXT: ret i64 [[ZEXT]] + %shl = shl i32 1, %y + %zext0 = zext i32 %shl to i64 + %zext1 = zext i32 %x to i64 + %urem = urem i64 %zext1, %zext0 + ret i64 %urem +}