From fa5a91a71ee3c62c6f0bc6cc1388175ad6f925c4 Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Fri, 21 Mar 2008 00:40:09 +0000 Subject: [PATCH] Undo 48570. Correctly match mmx shift instructions with an immediate operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48627 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/IntrinsicsX86.td | 24 --------------------- lib/Target/X86/X86InstrMMX.td | 40 +++++++++++++++++++++-------------- lib/VMCore/AutoUpgrade.cpp | 3 +-- test/CodeGen/X86/mmx-shift.ll | 4 ++-- 4 files changed, 27 insertions(+), 44 deletions(-) diff --git a/include/llvm/IntrinsicsX86.td b/include/llvm/IntrinsicsX86.td index e40097e897c..5bcfa7922ba 100644 --- a/include/llvm/IntrinsicsX86.td +++ b/include/llvm/IntrinsicsX86.td @@ -916,53 +916,29 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_mmx_psll_w : GCCBuiltin<"__builtin_ia32_psllw">, Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty, llvm_v1i64_ty], [IntrNoMem]>; - def int_x86_mmx_pslli_w : GCCBuiltin<"__builtin_ia32_psllwi">, - Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty, - llvm_i32_ty], [IntrNoMem]>; def int_x86_mmx_psll_d : GCCBuiltin<"__builtin_ia32_pslld">, Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty, llvm_v1i64_ty], [IntrNoMem]>; - def int_x86_mmx_pslli_d : GCCBuiltin<"__builtin_ia32_pslldi">, - Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty, - llvm_i32_ty], [IntrNoMem]>; def int_x86_mmx_psll_q : GCCBuiltin<"__builtin_ia32_psllq">, Intrinsic<[llvm_v1i64_ty, llvm_v1i64_ty, llvm_v1i64_ty], [IntrNoMem]>; - def int_x86_mmx_pslli_q : GCCBuiltin<"__builtin_ia32_psllqi">, - Intrinsic<[llvm_v1i64_ty, llvm_v1i64_ty, - llvm_i32_ty], [IntrNoMem]>; def int_x86_mmx_psrl_w : GCCBuiltin<"__builtin_ia32_psrlw">, Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty, llvm_v1i64_ty], [IntrNoMem]>; - def int_x86_mmx_psrli_w : GCCBuiltin<"__builtin_ia32_psrlwi">, - Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty, - llvm_i32_ty], [IntrNoMem]>; def int_x86_mmx_psrl_d : GCCBuiltin<"__builtin_ia32_psrld">, Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty, llvm_v1i64_ty], [IntrNoMem]>; - def int_x86_mmx_psrli_d : GCCBuiltin<"__builtin_ia32_psrldi">, - Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty, - llvm_i32_ty], [IntrNoMem]>; def int_x86_mmx_psrl_q : GCCBuiltin<"__builtin_ia32_psrlq">, Intrinsic<[llvm_v1i64_ty, llvm_v1i64_ty, llvm_v1i64_ty], [IntrNoMem]>; - def int_x86_mmx_psrli_q : GCCBuiltin<"__builtin_ia32_psrlqi">, - Intrinsic<[llvm_v1i64_ty, llvm_v1i64_ty, - llvm_i32_ty], [IntrNoMem]>; def int_x86_mmx_psra_w : GCCBuiltin<"__builtin_ia32_psraw">, Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty, llvm_v1i64_ty], [IntrNoMem]>; - def int_x86_mmx_psrai_w : GCCBuiltin<"__builtin_ia32_psrawi">, - Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty, - llvm_i32_ty], [IntrNoMem]>; def int_x86_mmx_psra_d : GCCBuiltin<"__builtin_ia32_psrad">, Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty, llvm_v1i64_ty], [IntrNoMem]>; - def int_x86_mmx_psrai_d : GCCBuiltin<"__builtin_ia32_psradi">, - Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty, - llvm_i32_ty], [IntrNoMem]>; } // Pack ops. diff --git a/lib/Target/X86/X86InstrMMX.td b/lib/Target/X86/X86InstrMMX.td index b079d17fd6c..407f8a6f199 100644 --- a/lib/Target/X86/X86InstrMMX.td +++ b/lib/Target/X86/X86InstrMMX.td @@ -104,30 +104,38 @@ let isTwoAddress = 1 in { // multiclass MMXI_binop_rm_v1i64 opc, string OpcodeStr, SDNode OpNode, bit Commutable = 0> { - def rr : MMXI { let isCommutable = Commutable; } - def rm : MMXI; } multiclass MMXI_binop_rmi_int opc, bits<8> opc2, Format ImmForm, - string OpcodeStr, Intrinsic IntId, - Intrinsic ImmIntId> { - def rr : MMXI { + def rr : MMXI; - def rm : MMXI; - def ri : MMXIi8; + [(set VR64:$dst, (IntId VR64:$src1, + (v1i64 (bitconvert + (v2i32 (vector_shuffle immAllZerosV, + (v2i32 (scalar_to_vector (i32 imm:$src2))), + MMX_MOVL_shuffle_mask))))))]>; } } @@ -268,23 +276,23 @@ let isTwoAddress = 1 in { // Shift Instructions defm MMX_PSRLW : MMXI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw", - int_x86_mmx_psrl_w, int_x86_mmx_psrli_w>; + int_x86_mmx_psrl_w>; defm MMX_PSRLD : MMXI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld", - int_x86_mmx_psrl_d, int_x86_mmx_psrli_d>; + int_x86_mmx_psrl_d>; defm MMX_PSRLQ : MMXI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq", - int_x86_mmx_psrl_q, int_x86_mmx_psrli_q>; + int_x86_mmx_psrl_q>; defm MMX_PSLLW : MMXI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw", - int_x86_mmx_psll_w, int_x86_mmx_pslli_w>; + int_x86_mmx_psll_w>; defm MMX_PSLLD : MMXI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld", - int_x86_mmx_psll_d, int_x86_mmx_pslli_d>; + int_x86_mmx_psll_d>; defm MMX_PSLLQ : MMXI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq", - int_x86_mmx_psll_q, int_x86_mmx_pslli_q>; + int_x86_mmx_psll_q>; defm MMX_PSRAW : MMXI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw", - int_x86_mmx_psra_w, int_x86_mmx_psrai_w>; + int_x86_mmx_psra_w>; defm MMX_PSRAD : MMXI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad", - int_x86_mmx_psra_d, int_x86_mmx_psrai_d>; + int_x86_mmx_psra_d>; // Comparison Instructions defm MMX_PCMPEQB : MMXI_binop_rm_int<0x74, "pcmpeqb", int_x86_mmx_pcmpeq_b>; diff --git a/lib/VMCore/AutoUpgrade.cpp b/lib/VMCore/AutoUpgrade.cpp index a46138a612b..343a4b6431b 100644 --- a/lib/VMCore/AutoUpgrade.cpp +++ b/lib/VMCore/AutoUpgrade.cpp @@ -122,8 +122,7 @@ static bool UpgradeIntrinsicFunction1(Function *F, Function *&NewFn) { if (Name.compare(5,10,"x86.mmx.ps",10) == 0 && (Name.compare(13,4,"psll", 4) == 0 || Name.compare(13,4,"psra", 4) == 0 || - Name.compare(13,4,"psrl", 4) == 0) && - Name[17] != 'i') { + Name.compare(13,4,"psrl", 4) == 0)) { const llvm::Type *VT = VectorType::get(IntegerType::get(64), 1); diff --git a/test/CodeGen/X86/mmx-shift.ll b/test/CodeGen/X86/mmx-shift.ll index 1ebc0435c81..d68af2d1d33 100644 --- a/test/CodeGen/X86/mmx-shift.ll +++ b/test/CodeGen/X86/mmx-shift.ll @@ -3,12 +3,12 @@ define i64 @t1(<1 x i64> %mm1) nounwind { entry: - %tmp6 = tail call <1 x i64> @llvm.x86.mmx.pslli.q( <1 x i64> %mm1, i32 32 ) ; <<1 x i64>> [#uses=1] + %tmp6 = tail call <1 x i64> @llvm.x86.mmx.psll.q( <1 x i64> %mm1, <1 x i64> ) ; <<1 x i64>> [#uses=1] %retval1112 = bitcast <1 x i64> %tmp6 to i64 ; [#uses=1] ret i64 %retval1112 } -declare <1 x i64> @llvm.x86.mmx.pslli.q(<1 x i64>, i32) nounwind readnone +declare <1 x i64> @llvm.x86.mmx.psll.q(<1 x i64>, <1 x i64>) nounwind readnone define i64 @t2(<2 x i32> %mm1, <2 x i32> %mm2) nounwind { entry: