From fa775d09c6bb506cf0696e0d688cafcb74955702 Mon Sep 17 00:00:00 2001
From: Evan Cheng <evan.cheng@apple.com>
Date: Mon, 19 Mar 2007 07:20:03 +0000
Subject: [PATCH] Special LDR instructions to load from non-pc-relative
 constantpools. These are rematerializable. Only used for constant generation
 for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35162 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/ARM/ARMISelDAGToDAG.cpp | 4 ++--
 lib/Target/ARM/ARMInstrInfo.td     | 5 +++++
 lib/Target/ARM/ARMInstrThumb.td    | 5 +++++
 3 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index b0c040b39d7..7c40a712212 100644
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -551,7 +551,7 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
 
       SDNode *ResNode;
       if (Subtarget->isThumb())
-        ResNode = CurDAG->getTargetNode(ARM::tLDRpci, MVT::i32, MVT::Other,
+        ResNode = CurDAG->getTargetNode(ARM::tLDRcp, MVT::i32, MVT::Other,
                                         CPIdx, CurDAG->getEntryNode());
       else {
         SDOperand Ops[] = {
@@ -560,7 +560,7 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
           CurDAG->getTargetConstant(0, MVT::i32),
           CurDAG->getEntryNode()
         };
-        ResNode = CurDAG->getTargetNode(ARM::LDR, MVT::i32, MVT::Other, Ops, 4);
+        ResNode=CurDAG->getTargetNode(ARM::LDRcp, MVT::i32, MVT::Other, Ops, 4);
       }
       ReplaceUses(Op, SDOperand(ResNode, 0));
       return NULL;
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index cb0a508bf93..b222c5b0ee9 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -580,6 +580,11 @@ def LDR  : AI2<(ops GPR:$dst, addrmode2:$addr),
                "ldr $dst, $addr",
                [(set GPR:$dst, (load addrmode2:$addr))]>;
 
+// Special LDR for loads from non-pc-relative constpools.
+let isReMaterializable = 1 in
+def LDRcp : AI2<(ops GPR:$dst, addrmode2:$addr),
+                 "ldr $dst, $addr", []>;
+
 // Loads with zero extension
 def LDRH  : AI3<(ops GPR:$dst, addrmode3:$addr),
                  "ldrh $dst, $addr",
diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td
index 6b289d9a051..a70bf96fd02 100644
--- a/lib/Target/ARM/ARMInstrThumb.td
+++ b/lib/Target/ARM/ARMInstrThumb.td
@@ -248,6 +248,11 @@ def tRestore : TIs<(ops GPR:$dst, t_addrmode_sp:$addr),
 def tLDRpci : TIs<(ops GPR:$dst, i32imm:$addr),
                   "ldr $dst, $addr",
                   [(set GPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>;
+
+// Special LDR for loads from non-pc-relative constpools.
+let isReMaterializable = 1 in
+def tLDRcp  : TIs<(ops GPR:$dst, i32imm:$addr),
+                  "ldr $dst, $addr", []>;
 } // isLoad
 
 let isStore = 1 in {