From faa6adf67c29e51d819e8ed9d2de0176cb0ab6fe Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Mon, 21 Sep 2009 06:04:07 +0000 Subject: [PATCH] add a note git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82442 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/README.txt | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/lib/Target/README.txt b/lib/Target/README.txt index 8ff08fbf036..89ea9d0afc4 100644 --- a/lib/Target/README.txt +++ b/lib/Target/README.txt @@ -220,7 +220,20 @@ so cool to turn it into something like: ... which would only do one 32-bit XOR per loop iteration instead of two. It would also be nice to recognize the reg->size doesn't alias reg->node[i], but -alas... +alas. + +//===---------------------------------------------------------------------===// + +This should be optimized to one 'and' and one 'or', from PR4216: + +define i32 @test_bitfield(i32 %bf.prev.low) nounwind ssp { +entry: + %bf.prev.lo.cleared10 = or i32 %bf.prev.low, 32962 ; [#uses=1] + %0 = and i32 %bf.prev.low, -65536 ; [#uses=1] + %1 = and i32 %bf.prev.lo.cleared10, 40186 ; [#uses=1] + %2 = or i32 %1, %0 ; [#uses=1] + ret i32 %2 +} //===---------------------------------------------------------------------===//