From fad04531a9ce9fa816f65ec8fc902e4392cfcb4b Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Tue, 6 Jan 2015 19:52:04 +0000 Subject: [PATCH] R600/SI: Fix dependency calculation for DS writes instructions in SIInsertWaits In DS write instructions, the address operand comes before the value operand(s) which is reversed from every other instruction type. The SIInsertWait assumed that the first use for each instruction was the value, so for DS write it was protecting the address operand with s_waitcnt instructions when it should have been protecting the value operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225289 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/R600/SIInsertWaits.cpp | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/lib/Target/R600/SIInsertWaits.cpp b/lib/Target/R600/SIInsertWaits.cpp index f279e5e5c58..2e56508e2fa 100644 --- a/lib/Target/R600/SIInsertWaits.cpp +++ b/lib/Target/R600/SIInsertWaits.cpp @@ -186,6 +186,29 @@ bool SIInsertWaits::isOpRelevant(MachineOperand &Op) { if (!MI.getDesc().mayStore()) return false; + // Check if this operand is the value being stored. + // Special case for DS instructions, since the address + // operand comes before the value operand and it may have + // multiple data operands. + + if (TII->isDS(MI.getOpcode())) { + MachineOperand *Data = TII->getNamedOperand(MI, AMDGPU::OpName::data); + if (Data && Op.isIdenticalTo(*Data)) + return true; + + MachineOperand *Data0 = TII->getNamedOperand(MI, AMDGPU::OpName::data0); + if (Data0 && Op.isIdenticalTo(*Data0)) + return true; + + MachineOperand *Data1 = TII->getNamedOperand(MI, AMDGPU::OpName::data1); + if (Data1 && Op.isIdenticalTo(*Data1)) + return true; + + return false; + } + + // NOTE: This assumes that the value operand is before the + // address operand, and that there is only one value operand. for (MachineInstr::mop_iterator I = MI.operands_begin(), E = MI.operands_end(); I != E; ++I) {