mirror of
https://github.com/c64scene-ar/llvm-6502.git
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AArch64/ARM64: port basic disassembly tests to ARM64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207753 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover
parent
f2f35a9ca3
commit
fadbf53e7e
@ -1,4 +1,5 @@
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# RUN: llvm-mc -triple=aarch64 -mattr=fp-armv8 -disassemble -show-encoding < %s | FileCheck %s
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# RUN: llvm-mc -triple=arm64 -mattr=fp-armv8 -disassemble -show-encoding < %s | FileCheck %s
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# The "Rm" bits are ignored, but the canonical representation has them filled
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# with 0s. This is what we should produce even if the input bit-pattern had
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File diff suppressed because it is too large
Load Diff
@ -1,222 +1,223 @@
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# RUN: llvm-mc -triple aarch64-none-linux-gnu -disassemble < %s | FileCheck %s
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# RUN: llvm-mc -triple arm64-none-linux-gnu -disassemble < %s | FileCheck %s
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0x8 0xcc 0x38 0xd5
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# CHECK: mrs x8, icc_iar1_el1
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# CHECK: mrs x8, {{icc_iar1_el1|ICC_IAR1_EL1}}
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0x1a 0xc8 0x38 0xd5
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# CHECK: mrs x26, icc_iar0_el1
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# CHECK: mrs x26, {{icc_iar0_el1|ICC_IAR0_EL1}}
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0x42 0xcc 0x38 0xd5
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# CHECK: mrs x2, icc_hppir1_el1
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# CHECK: mrs x2, {{icc_hppir1_el1|ICC_HPPIR1_EL1}}
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0x51 0xc8 0x38 0xd5
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# CHECK: mrs x17, icc_hppir0_el1
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# CHECK: mrs x17, {{icc_hppir0_el1|ICC_HPPIR0_EL1}}
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0x7d 0xcb 0x38 0xd5
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# CHECK: mrs x29, icc_rpr_el1
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# CHECK: mrs x29, {{icc_rpr_el1|ICC_RPR_EL1}}
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0x24 0xcb 0x3c 0xd5
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# CHECK: mrs x4, ich_vtr_el2
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# CHECK: mrs x4, {{ich_vtr_el2|ICH_VTR_EL2}}
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0x78 0xcb 0x3c 0xd5
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# CHECK: mrs x24, ich_eisr_el2
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# CHECK: mrs x24, {{ich_eisr_el2|ICH_EISR_EL2}}
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0xa9 0xcb 0x3c 0xd5
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# CHECK: mrs x9, ich_elsr_el2
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# CHECK: mrs x9, {{ich_elsr_el2|ICH_ELSR_EL2}}
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0x78 0xcc 0x38 0xd5
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# CHECK: mrs x24, icc_bpr1_el1
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# CHECK: mrs x24, {{icc_bpr1_el1|ICC_BPR1_EL1}}
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0x6e 0xc8 0x38 0xd5
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# CHECK: mrs x14, icc_bpr0_el1
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# CHECK: mrs x14, {{icc_bpr0_el1|ICC_BPR0_EL1}}
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0x13 0x46 0x38 0xd5
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# CHECK: mrs x19, icc_pmr_el1
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# CHECK: mrs x19, {{icc_pmr_el1|ICC_PMR_EL1}}
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0x97 0xcc 0x38 0xd5
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# CHECK: mrs x23, icc_ctlr_el1
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# CHECK: mrs x23, {{icc_ctlr_el1|ICC_CTLR_EL1}}
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0x94 0xcc 0x3e 0xd5
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# CHECK: mrs x20, icc_ctlr_el3
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# CHECK: mrs x20, {{icc_ctlr_el3|ICC_CTLR_EL3}}
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0xbc 0xcc 0x38 0xd5
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# CHECK: mrs x28, icc_sre_el1
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# CHECK: mrs x28, {{icc_sre_el1|ICC_SRE_EL1}}
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0xb9 0xc9 0x3c 0xd5
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# CHECK: mrs x25, icc_sre_el2
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# CHECK: mrs x25, {{icc_sre_el2|ICC_SRE_EL2}}
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0xa8 0xcc 0x3e 0xd5
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# CHECK: mrs x8, icc_sre_el3
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# CHECK: mrs x8, {{icc_sre_el3|ICC_SRE_EL3}}
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0xd6 0xcc 0x38 0xd5
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# CHECK: mrs x22, icc_igrpen0_el1
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# CHECK: mrs x22, {{icc_igrpen0_el1|ICC_IGRPEN0_EL1}}
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0xe5 0xcc 0x38 0xd5
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# CHECK: mrs x5, icc_igrpen1_el1
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# CHECK: mrs x5, {{icc_igrpen1_el1|ICC_IGRPEN1_EL1}}
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0xe7 0xcc 0x3e 0xd5
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# CHECK: mrs x7, icc_igrpen1_el3
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# CHECK: mrs x7, {{icc_igrpen1_el3|ICC_IGRPEN1_EL3}}
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0x16 0xcd 0x38 0xd5
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# CHECK: mrs x22, icc_seien_el1
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# CHECK: mrs x22, {{icc_seien_el1|ICC_SEIEN_EL1}}
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0x84 0xc8 0x38 0xd5
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# CHECK: mrs x4, icc_ap0r0_el1
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# CHECK: mrs x4, {{icc_ap0r0_el1|ICC_AP0R0_EL1}}
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0xab 0xc8 0x38 0xd5
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# CHECK: mrs x11, icc_ap0r1_el1
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# CHECK: mrs x11, {{icc_ap0r1_el1|ICC_AP0R1_EL1}}
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0xdb 0xc8 0x38 0xd5
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# CHECK: mrs x27, icc_ap0r2_el1
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# CHECK: mrs x27, {{icc_ap0r2_el1|ICC_AP0R2_EL1}}
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0xf5 0xc8 0x38 0xd5
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# CHECK: mrs x21, icc_ap0r3_el1
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# CHECK: mrs x21, {{icc_ap0r3_el1|ICC_AP0R3_EL1}}
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0x2 0xc9 0x38 0xd5
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# CHECK: mrs x2, icc_ap1r0_el1
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# CHECK: mrs x2, {{icc_ap1r0_el1|ICC_AP1R0_EL1}}
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0x35 0xc9 0x38 0xd5
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# CHECK: mrs x21, icc_ap1r1_el1
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# CHECK: mrs x21, {{icc_ap1r1_el1|ICC_AP1R1_EL1}}
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0x4a 0xc9 0x38 0xd5
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# CHECK: mrs x10, icc_ap1r2_el1
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# CHECK: mrs x10, {{icc_ap1r2_el1|ICC_AP1R2_EL1}}
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0x7b 0xc9 0x38 0xd5
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# CHECK: mrs x27, icc_ap1r3_el1
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# CHECK: mrs x27, {{icc_ap1r3_el1|ICC_AP1R3_EL1}}
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0x14 0xc8 0x3c 0xd5
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# CHECK: mrs x20, ich_ap0r0_el2
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# CHECK: mrs x20, {{ich_ap0r0_el2|ICH_AP0R0_EL2}}
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0x35 0xc8 0x3c 0xd5
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# CHECK: mrs x21, ich_ap0r1_el2
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# CHECK: mrs x21, {{ich_ap0r1_el2|ICH_AP0R1_EL2}}
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0x45 0xc8 0x3c 0xd5
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# CHECK: mrs x5, ich_ap0r2_el2
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# CHECK: mrs x5, {{ich_ap0r2_el2|ICH_AP0R2_EL2}}
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0x64 0xc8 0x3c 0xd5
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# CHECK: mrs x4, ich_ap0r3_el2
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# CHECK: mrs x4, {{ich_ap0r3_el2|ICH_AP0R3_EL2}}
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0xf 0xc9 0x3c 0xd5
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# CHECK: mrs x15, ich_ap1r0_el2
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# CHECK: mrs x15, {{ich_ap1r0_el2|ICH_AP1R0_EL2}}
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0x2c 0xc9 0x3c 0xd5
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# CHECK: mrs x12, ich_ap1r1_el2
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# CHECK: mrs x12, {{ich_ap1r1_el2|ICH_AP1R1_EL2}}
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0x5b 0xc9 0x3c 0xd5
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# CHECK: mrs x27, ich_ap1r2_el2
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# CHECK: mrs x27, {{ich_ap1r2_el2|ICH_AP1R2_EL2}}
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0x74 0xc9 0x3c 0xd5
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# CHECK: mrs x20, ich_ap1r3_el2
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# CHECK: mrs x20, {{ich_ap1r3_el2|ICH_AP1R3_EL2}}
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0xa 0xcb 0x3c 0xd5
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# CHECK: mrs x10, ich_hcr_el2
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# CHECK: mrs x10, {{ich_hcr_el2|ICH_HCR_EL2}}
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0x5b 0xcb 0x3c 0xd5
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# CHECK: mrs x27, ich_misr_el2
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# CHECK: mrs x27, {{ich_misr_el2|ICH_MISR_EL2}}
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0xe6 0xcb 0x3c 0xd5
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# CHECK: mrs x6, ich_vmcr_el2
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# CHECK: mrs x6, {{ich_vmcr_el2|ICH_VMCR_EL2}}
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0x93 0xc9 0x3c 0xd5
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# CHECK: mrs x19, ich_vseir_el2
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# CHECK: mrs x19, {{ich_vseir_el2|ICH_VSEIR_EL2}}
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0x3 0xcc 0x3c 0xd5
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# CHECK: mrs x3, ich_lr0_el2
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# CHECK: mrs x3, {{ich_lr0_el2|ICH_LR0_EL2}}
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0x21 0xcc 0x3c 0xd5
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# CHECK: mrs x1, ich_lr1_el2
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# CHECK: mrs x1, {{ich_lr1_el2|ICH_LR1_EL2}}
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0x56 0xcc 0x3c 0xd5
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# CHECK: mrs x22, ich_lr2_el2
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# CHECK: mrs x22, {{ich_lr2_el2|ICH_LR2_EL2}}
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0x75 0xcc 0x3c 0xd5
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# CHECK: mrs x21, ich_lr3_el2
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# CHECK: mrs x21, {{ich_lr3_el2|ICH_LR3_EL2}}
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0x86 0xcc 0x3c 0xd5
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# CHECK: mrs x6, ich_lr4_el2
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# CHECK: mrs x6, {{ich_lr4_el2|ICH_LR4_EL2}}
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0xaa 0xcc 0x3c 0xd5
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# CHECK: mrs x10, ich_lr5_el2
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# CHECK: mrs x10, {{ich_lr5_el2|ICH_LR5_EL2}}
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0xcb 0xcc 0x3c 0xd5
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# CHECK: mrs x11, ich_lr6_el2
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# CHECK: mrs x11, {{ich_lr6_el2|ICH_LR6_EL2}}
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0xec 0xcc 0x3c 0xd5
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# CHECK: mrs x12, ich_lr7_el2
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# CHECK: mrs x12, {{ich_lr7_el2|ICH_LR7_EL2}}
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0x0 0xcd 0x3c 0xd5
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# CHECK: mrs x0, ich_lr8_el2
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# CHECK: mrs x0, {{ich_lr8_el2|ICH_LR8_EL2}}
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0x35 0xcd 0x3c 0xd5
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# CHECK: mrs x21, ich_lr9_el2
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# CHECK: mrs x21, {{ich_lr9_el2|ICH_LR9_EL2}}
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0x4d 0xcd 0x3c 0xd5
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# CHECK: mrs x13, ich_lr10_el2
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# CHECK: mrs x13, {{ich_lr10_el2|ICH_LR10_EL2}}
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0x7a 0xcd 0x3c 0xd5
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# CHECK: mrs x26, ich_lr11_el2
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# CHECK: mrs x26, {{ich_lr11_el2|ICH_LR11_EL2}}
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0x81 0xcd 0x3c 0xd5
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# CHECK: mrs x1, ich_lr12_el2
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# CHECK: mrs x1, {{ich_lr12_el2|ICH_LR12_EL2}}
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0xa8 0xcd 0x3c 0xd5
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# CHECK: mrs x8, ich_lr13_el2
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# CHECK: mrs x8, {{ich_lr13_el2|ICH_LR13_EL2}}
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0xc2 0xcd 0x3c 0xd5
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# CHECK: mrs x2, ich_lr14_el2
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# CHECK: mrs x2, {{ich_lr14_el2|ICH_LR14_EL2}}
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0xe8 0xcd 0x3c 0xd5
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# CHECK: mrs x8, ich_lr15_el2
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# CHECK: mrs x8, {{ich_lr15_el2|ICH_LR15_EL2}}
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0x3b 0xcc 0x18 0xd5
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# CHECK: msr icc_eoir1_el1, x27
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# CHECK: msr {{icc_eoir1_el1|ICC_EOIR1_EL1}}, x27
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0x25 0xc8 0x18 0xd5
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# CHECK: msr icc_eoir0_el1, x5
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# CHECK: msr {{icc_eoir0_el1|ICC_EOIR0_EL1}}, x5
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0x2d 0xcb 0x18 0xd5
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# CHECK: msr icc_dir_el1, x13
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# CHECK: msr {{icc_dir_el1|ICC_DIR_EL1}}, x13
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0xb5 0xcb 0x18 0xd5
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# CHECK: msr icc_sgi1r_el1, x21
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# CHECK: msr {{icc_sgi1r_el1|ICC_SGI1R_EL1}}, x21
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0xd9 0xcb 0x18 0xd5
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# CHECK: msr icc_asgi1r_el1, x25
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# CHECK: msr {{icc_asgi1r_el1|ICC_ASGI1R_EL1}}, x25
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0xfc 0xcb 0x18 0xd5
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# CHECK: msr icc_sgi0r_el1, x28
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# CHECK: msr {{icc_sgi0r_el1|ICC_SGI0R_EL1}}, x28
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0x67 0xcc 0x18 0xd5
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# CHECK: msr icc_bpr1_el1, x7
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# CHECK: msr {{icc_bpr1_el1|ICC_BPR1_EL1}}, x7
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0x69 0xc8 0x18 0xd5
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# CHECK: msr icc_bpr0_el1, x9
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# CHECK: msr {{icc_bpr0_el1|ICC_BPR0_EL1}}, x9
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0x1d 0x46 0x18 0xd5
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# CHECK: msr icc_pmr_el1, x29
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# CHECK: msr {{icc_pmr_el1|ICC_PMR_EL1}}, x29
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0x98 0xcc 0x18 0xd5
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# CHECK: msr icc_ctlr_el1, x24
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# CHECK: msr {{icc_ctlr_el1|ICC_CTLR_EL1}}, x24
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0x80 0xcc 0x1e 0xd5
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# CHECK: msr icc_ctlr_el3, x0
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# CHECK: msr {{icc_ctlr_el3|ICC_CTLR_EL3}}, x0
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0xa2 0xcc 0x18 0xd5
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# CHECK: msr icc_sre_el1, x2
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# CHECK: msr {{icc_sre_el1|ICC_SRE_EL1}}, x2
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0xa5 0xc9 0x1c 0xd5
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# CHECK: msr icc_sre_el2, x5
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# CHECK: msr {{icc_sre_el2|ICC_SRE_EL2}}, x5
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0xaa 0xcc 0x1e 0xd5
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# CHECK: msr icc_sre_el3, x10
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# CHECK: msr {{icc_sre_el3|ICC_SRE_EL3}}, x10
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0xd6 0xcc 0x18 0xd5
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# CHECK: msr icc_igrpen0_el1, x22
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# CHECK: msr {{icc_igrpen0_el1|ICC_IGRPEN0_EL1}}, x22
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0xeb 0xcc 0x18 0xd5
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# CHECK: msr icc_igrpen1_el1, x11
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# CHECK: msr {{icc_igrpen1_el1|ICC_IGRPEN1_EL1}}, x11
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0xe8 0xcc 0x1e 0xd5
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# CHECK: msr icc_igrpen1_el3, x8
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# CHECK: msr {{icc_igrpen1_el3|ICC_IGRPEN1_EL3}}, x8
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0x4 0xcd 0x18 0xd5
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# CHECK: msr icc_seien_el1, x4
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# CHECK: msr {{icc_seien_el1|ICC_SEIEN_EL1}}, x4
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0x9b 0xc8 0x18 0xd5
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# CHECK: msr icc_ap0r0_el1, x27
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# CHECK: msr {{icc_ap0r0_el1|ICC_AP0R0_EL1}}, x27
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0xa5 0xc8 0x18 0xd5
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# CHECK: msr icc_ap0r1_el1, x5
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# CHECK: msr {{icc_ap0r1_el1|ICC_AP0R1_EL1}}, x5
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0xd4 0xc8 0x18 0xd5
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# CHECK: msr icc_ap0r2_el1, x20
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# CHECK: msr {{icc_ap0r2_el1|ICC_AP0R2_EL1}}, x20
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0xe0 0xc8 0x18 0xd5
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# CHECK: msr icc_ap0r3_el1, x0
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# CHECK: msr {{icc_ap0r3_el1|ICC_AP0R3_EL1}}, x0
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0x2 0xc9 0x18 0xd5
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# CHECK: msr icc_ap1r0_el1, x2
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# CHECK: msr {{icc_ap1r0_el1|ICC_AP1R0_EL1}}, x2
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0x3d 0xc9 0x18 0xd5
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# CHECK: msr icc_ap1r1_el1, x29
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# CHECK: msr {{icc_ap1r1_el1|ICC_AP1R1_EL1}}, x29
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0x57 0xc9 0x18 0xd5
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# CHECK: msr icc_ap1r2_el1, x23
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# CHECK: msr {{icc_ap1r2_el1|ICC_AP1R2_EL1}}, x23
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0x6b 0xc9 0x18 0xd5
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# CHECK: msr icc_ap1r3_el1, x11
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# CHECK: msr {{icc_ap1r3_el1|ICC_AP1R3_EL1}}, x11
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0x2 0xc8 0x1c 0xd5
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# CHECK: msr ich_ap0r0_el2, x2
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# CHECK: msr {{ich_ap0r0_el2|ICH_AP0R0_EL2}}, x2
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0x3b 0xc8 0x1c 0xd5
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# CHECK: msr ich_ap0r1_el2, x27
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# CHECK: msr {{ich_ap0r1_el2|ICH_AP0R1_EL2}}, x27
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0x47 0xc8 0x1c 0xd5
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# CHECK: msr ich_ap0r2_el2, x7
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# CHECK: msr {{ich_ap0r2_el2|ICH_AP0R2_EL2}}, x7
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0x61 0xc8 0x1c 0xd5
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# CHECK: msr ich_ap0r3_el2, x1
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# CHECK: msr {{ich_ap0r3_el2|ICH_AP0R3_EL2}}, x1
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0x7 0xc9 0x1c 0xd5
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# CHECK: msr ich_ap1r0_el2, x7
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# CHECK: msr {{ich_ap1r0_el2|ICH_AP1R0_EL2}}, x7
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0x2c 0xc9 0x1c 0xd5
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# CHECK: msr ich_ap1r1_el2, x12
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# CHECK: msr {{ich_ap1r1_el2|ICH_AP1R1_EL2}}, x12
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0x4e 0xc9 0x1c 0xd5
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# CHECK: msr ich_ap1r2_el2, x14
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# CHECK: msr {{ich_ap1r2_el2|ICH_AP1R2_EL2}}, x14
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0x6d 0xc9 0x1c 0xd5
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# CHECK: msr ich_ap1r3_el2, x13
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# CHECK: msr {{ich_ap1r3_el2|ICH_AP1R3_EL2}}, x13
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0x1 0xcb 0x1c 0xd5
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# CHECK: msr ich_hcr_el2, x1
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# CHECK: msr {{ich_hcr_el2|ICH_HCR_EL2}}, x1
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0x4a 0xcb 0x1c 0xd5
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# CHECK: msr ich_misr_el2, x10
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# CHECK: msr {{ich_misr_el2|ICH_MISR_EL2}}, x10
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0xf8 0xcb 0x1c 0xd5
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# CHECK: msr ich_vmcr_el2, x24
|
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# CHECK: msr {{ich_vmcr_el2|ICH_VMCR_EL2}}, x24
|
||||
0x9d 0xc9 0x1c 0xd5
|
||||
# CHECK: msr ich_vseir_el2, x29
|
||||
# CHECK: msr {{ich_vseir_el2|ICH_VSEIR_EL2}}, x29
|
||||
0x1a 0xcc 0x1c 0xd5
|
||||
# CHECK: msr ich_lr0_el2, x26
|
||||
# CHECK: msr {{ich_lr0_el2|ICH_LR0_EL2}}, x26
|
||||
0x29 0xcc 0x1c 0xd5
|
||||
# CHECK: msr ich_lr1_el2, x9
|
||||
# CHECK: msr {{ich_lr1_el2|ICH_LR1_EL2}}, x9
|
||||
0x52 0xcc 0x1c 0xd5
|
||||
# CHECK: msr ich_lr2_el2, x18
|
||||
# CHECK: msr {{ich_lr2_el2|ICH_LR2_EL2}}, x18
|
||||
0x7a 0xcc 0x1c 0xd5
|
||||
# CHECK: msr ich_lr3_el2, x26
|
||||
# CHECK: msr {{ich_lr3_el2|ICH_LR3_EL2}}, x26
|
||||
0x96 0xcc 0x1c 0xd5
|
||||
# CHECK: msr ich_lr4_el2, x22
|
||||
# CHECK: msr {{ich_lr4_el2|ICH_LR4_EL2}}, x22
|
||||
0xba 0xcc 0x1c 0xd5
|
||||
# CHECK: msr ich_lr5_el2, x26
|
||||
# CHECK: msr {{ich_lr5_el2|ICH_LR5_EL2}}, x26
|
||||
0xdb 0xcc 0x1c 0xd5
|
||||
# CHECK: msr ich_lr6_el2, x27
|
||||
# CHECK: msr {{ich_lr6_el2|ICH_LR6_EL2}}, x27
|
||||
0xe8 0xcc 0x1c 0xd5
|
||||
# CHECK: msr ich_lr7_el2, x8
|
||||
# CHECK: msr {{ich_lr7_el2|ICH_LR7_EL2}}, x8
|
||||
0x11 0xcd 0x1c 0xd5
|
||||
# CHECK: msr ich_lr8_el2, x17
|
||||
# CHECK: msr {{ich_lr8_el2|ICH_LR8_EL2}}, x17
|
||||
0x33 0xcd 0x1c 0xd5
|
||||
# CHECK: msr ich_lr9_el2, x19
|
||||
# CHECK: msr {{ich_lr9_el2|ICH_LR9_EL2}}, x19
|
||||
0x51 0xcd 0x1c 0xd5
|
||||
# CHECK: msr ich_lr10_el2, x17
|
||||
# CHECK: msr {{ich_lr10_el2|ICH_LR10_EL2}}, x17
|
||||
0x65 0xcd 0x1c 0xd5
|
||||
# CHECK: msr ich_lr11_el2, x5
|
||||
# CHECK: msr {{ich_lr11_el2|ICH_LR11_EL2}}, x5
|
||||
0x9d 0xcd 0x1c 0xd5
|
||||
# CHECK: msr ich_lr12_el2, x29
|
||||
# CHECK: msr {{ich_lr12_el2|ICH_LR12_EL2}}, x29
|
||||
0xa2 0xcd 0x1c 0xd5
|
||||
# CHECK: msr ich_lr13_el2, x2
|
||||
# CHECK: msr {{ich_lr13_el2|ICH_LR13_EL2}}, x2
|
||||
0xcd 0xcd 0x1c 0xd5
|
||||
# CHECK: msr ich_lr14_el2, x13
|
||||
# CHECK: msr {{ich_lr14_el2|ICH_LR14_EL2}}, x13
|
||||
0xfb 0xcd 0x1c 0xd5
|
||||
# CHECK: msr ich_lr15_el2, x27
|
||||
# CHECK: msr {{ich_lr15_el2|ICH_LR15_EL2}}, x27
|
||||
|
||||
@ -1,4 +1,5 @@
|
||||
# RUN: llvm-mc -triple=aarch64 -disassemble < %s 2>&1 | FileCheck %s
|
||||
# RUN: llvm-mc -triple=arm64 -disassemble < %s 2>&1 | FileCheck %s
|
||||
|
||||
# Stores are OK.
|
||||
0xe0 0x83 0x00 0xa9
|
||||
|
||||
@ -1,4 +1,5 @@
|
||||
# RUN: llvm-mc -triple=aarch64 -mattr=+fp-armv8 -disassemble < %s 2>&1 | FileCheck %s
|
||||
# RUN: llvm-mc -triple=arm64 -mattr=+fp-armv8 -disassemble < %s 2>&1 | FileCheck %s
|
||||
|
||||
# None of these instructions should be classified as unpredictable:
|
||||
|
||||
|
||||
@ -1,4 +1,5 @@
|
||||
# RUN: llvm-mc -triple=aarch64 -mattr=+fp-armv8 -disassemble < %s 2>&1 | FileCheck %s
|
||||
# RUN: llvm-mc -triple=arm64 -mattr=+fp-armv8 -disassemble < %s 2>&1 | FileCheck %s
|
||||
|
||||
# None of these instructions should be classified as unpredictable:
|
||||
|
||||
|
||||
@ -1,4 +1,5 @@
|
||||
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -disassemble < %s | FileCheck %s
|
||||
# RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -disassemble < %s | FileCheck %s
|
||||
|
||||
#------------------------------------------------------------------------------
|
||||
# Vector Integer Add/Sub
|
||||
@ -87,7 +88,7 @@
|
||||
# Vector Bitwise OR - immedidate
|
||||
#------------------------------------------------------------------------------
|
||||
# CHECK: movi v31.4s, #0xff, lsl #24
|
||||
# CHECK: mvni v0.2s, #0x0
|
||||
# CHECK: mvni v0.2s, #{{0x0|0}}
|
||||
# CHECK: bic v15.4h, #0xf, lsl #8
|
||||
# CHECK: orr v16.8h, #0x1f
|
||||
0xff 0x67 0x07 0x4f
|
||||
@ -246,31 +247,31 @@
|
||||
#----------------------------------------------------------------------
|
||||
# Vector Compare Mask Equal to Zero (Integer)
|
||||
#----------------------------------------------------------------------
|
||||
# CHECK: cmeq v31.16b, v15.16b, #0x0
|
||||
# CHECK: cmeq v31.16b, v15.16b, #{{0x0|0}}
|
||||
0xff 0x99 0x20 0x4e
|
||||
|
||||
#----------------------------------------------------------------------
|
||||
# Vector Compare Mask Greater Than or Equal to Zero (Signed Integer)
|
||||
#----------------------------------------------------------------------
|
||||
# CHECK: cmge v3.8b, v15.8b, #0x0
|
||||
# CHECK: cmge v3.8b, v15.8b, #{{0x0|0}}
|
||||
0xe3 0x89 0x20 0x2e
|
||||
|
||||
#----------------------------------------------------------------------
|
||||
# Vector Compare Mask Greater Than Zero (Signed Integer)
|
||||
#----------------------------------------------------------------------
|
||||
# CHECK: cmgt v22.2s, v9.2s, #0x0
|
||||
# CHECK: cmgt v22.2s, v9.2s, #{{0x0|0}}
|
||||
0x36 0x89 0xa0 0x0e
|
||||
|
||||
#----------------------------------------------------------------------
|
||||
# Vector Compare Mask Less Than or Equal To Zero (Signed Integer)
|
||||
#----------------------------------------------------------------------
|
||||
# CHECK: cmle v5.2d, v14.2d, #0x0
|
||||
# CHECK: cmle v5.2d, v14.2d, #{{0x0|0}}
|
||||
0xc5 0x99 0xe0 0x6e
|
||||
|
||||
#----------------------------------------------------------------------
|
||||
# Vector Compare Mask Less Than Zero (Signed Integer)
|
||||
#----------------------------------------------------------------------
|
||||
# CHECK: cmlt v13.8h, v11.8h, #0x0
|
||||
# CHECK: cmlt v13.8h, v11.8h, #{{0x0|0}}
|
||||
0x6d 0xa9 0x60 0x4e
|
||||
|
||||
#----------------------------------------------------------------------
|
||||
@ -1559,7 +1560,7 @@
|
||||
#----------------------------------------------------------------------
|
||||
# Scalar Compare Bitwise Equal To Zero
|
||||
#----------------------------------------------------------------------
|
||||
# CHECK: cmeq d20, d21, #0x0
|
||||
# CHECK: cmeq d20, d21, #{{0x0|0}}
|
||||
0xb4,0x9a,0xe0,0x5e
|
||||
|
||||
#----------------------------------------------------------------------
|
||||
@ -1578,7 +1579,7 @@
|
||||
#----------------------------------------------------------------------
|
||||
# Scalar Compare Signed Greather Than Or Equal To Zero
|
||||
#----------------------------------------------------------------------
|
||||
# CHECK: cmge d20, d21, #0x0
|
||||
# CHECK: cmge d20, d21, #{{0x0|0}}
|
||||
0xb4,0x8a,0xe0,0x7e
|
||||
|
||||
#----------------------------------------------------------------------
|
||||
@ -1596,19 +1597,19 @@
|
||||
#----------------------------------------------------------------------
|
||||
# Scalar Compare Signed Greater Than Zero
|
||||
#----------------------------------------------------------------------
|
||||
# CHECK: cmgt d20, d21, #0x0
|
||||
# CHECK: cmgt d20, d21, #{{0x0|0}}
|
||||
0xb4,0x8a,0xe0,0x5e
|
||||
|
||||
#----------------------------------------------------------------------
|
||||
# Scalar Compare Signed Less Than Or Equal To Zero
|
||||
#----------------------------------------------------------------------
|
||||
# CHECK: cmle d20, d21, #0x0
|
||||
# CHECK: cmle d20, d21, #{{0x0|0}}
|
||||
0xb4,0x9a,0xe0,0x7e
|
||||
|
||||
#----------------------------------------------------------------------
|
||||
# Scalar Compare Less Than Zero
|
||||
#----------------------------------------------------------------------
|
||||
# CHECK: cmlt d20, d21, #0x0
|
||||
# CHECK: cmlt d20, d21, #{{0x0|0}}
|
||||
0xb4,0xaa,0xe0,0x5e
|
||||
|
||||
#----------------------------------------------------------------------
|
||||
@ -2167,8 +2168,8 @@
|
||||
#----------------------------------------------------------------------
|
||||
0x20,0x18,0x02,0x2e
|
||||
0x20,0x18,0x02,0x6e
|
||||
# CHECK: ext v0.8b, v1.8b, v2.8b, #0x3
|
||||
# CHECK: ext v0.16b, v1.16b, v2.16b, #0x3
|
||||
# CHECK: ext v0.8b, v1.8b, v2.8b, #{{0x3|3}}
|
||||
# CHECK: ext v0.16b, v1.16b, v2.16b, #{{0x3|3}}
|
||||
|
||||
#----------------------------------------------------------------------
|
||||
# unzip with 3 same vectors to get primary result
|
||||
@ -2481,10 +2482,10 @@
|
||||
#----------------------------------------------------------------------
|
||||
#Duplicate element (scalar)
|
||||
#----------------------------------------------------------------------
|
||||
# CHECK: dup b0, v0.b[15]
|
||||
# CHECK: dup h2, v31.h[5]
|
||||
# CHECK: dup s17, v2.s[2]
|
||||
# CHECK: dup d6, v12.d[1]
|
||||
# CHECK: {{dup|mov}} b0, v0.b[15]
|
||||
# CHECK: {{dup|mov}} h2, v31.h[5]
|
||||
# CHECK: {{dup|mov}} s17, v2.s[2]
|
||||
# CHECK: {{dup|mov}} d6, v12.d[1]
|
||||
0x00 0x04 0x1f 0x5e
|
||||
0xe2 0x07 0x16 0x5e
|
||||
0x51 0x04 0x14 0x5e
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user