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X86: Fixed assertion failure in 32-bit mode

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The DAG Node "SCALAR_TO_VECTOR" may be created if the type of the scalar element is legal.
Added a check for the scalar type before creating this node.
Added a test that fails with assertion on the current version.

Differential Revision: http://reviews.llvm.org/D11413



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242994 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Elena Demikhovsky 2015-07-23 08:25:23 +00:00
parent fe6b5aa191
commit fb09d25df5
2 changed files with 14 additions and 2 deletions
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5
lib/Target/X86/X86ISelLowering.cpp
View File

@ -7380,8 +7380,9 @@ static SDValue lowerVectorShuffleAsElementInsertion(
// all the smarts here sunk into that routine. However, the current
// lowering of BUILD_VECTOR makes that nearly impossible until the old
// vector shuffle lowering is dead.
if (SDValue V2S = getScalarValueForVectorElement(
V2, Mask[V2Index] - Mask.size(), DAG)) {
SDValue V2S = getScalarValueForVectorElement(V2, Mask[V2Index] - Mask.size(),
DAG);
if (V2S && DAG.getTargetLoweringInfo().isTypeLegal(V2S.getValueType())) {
// We need to zext the scalar if it is smaller than an i32.
V2S = DAG.getBitcast(EltVT, V2S);
if (EltVT == MVT::i8 || EltVT == MVT::i16) {

11
test/CodeGen/X86/avx-shuffle-x86_32.ll
View File

@ -6,3 +6,14 @@ define <4 x i64> @test1(<4 x i64> %a) nounwind {
; CHECK-LABEL: test1:
; CHECK-NOT: vinsertf128
}
define <8 x i16> @test2(<4 x i16>* %v) nounwind {
; CHECK-LABEL: test2
; CHECK: vmovsd
; CHECK: vmovq
%v9 = load <4 x i16>, <4 x i16> * %v, align 8
%v10 = shufflevector <4 x i16> %v9, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
%v11 = shufflevector <8 x i16> <i16 undef, i16 undef, i16 undef, i16 undef, i16 0, i16 0, i16 0, i16 0>, <8 x i16> %v10, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7>
ret <8 x i16> %v11
}