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https://github.com/c64scene-ar/llvm-6502.git
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Model inline asm constraint which ties an input to an output register as machine operand TIED_TO constraint. This eliminated the need to pre-allocate registers for these. This also allows register allocator can eliminate the unneeded copies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67512 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -135,14 +135,13 @@ public:
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return (Flag & 0xffff) >> 3;
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}
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/// isOutputOperandTiedToUse - Return true if the flag of the inline asm
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/// operand indicates it is an output that's matched to an input operand.
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static bool isOutputOperandTiedToUse(unsigned Flag, unsigned &UseIdx) {
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if (Flag & 0x80000000) {
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UseIdx = Flag >> 16;
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return true;
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}
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return false;
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/// isUseOperandTiedToDef - Return true if the flag of the inline asm
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/// operand indicates it is an use operand that's matched to a def operand.
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static bool isUseOperandTiedToDef(unsigned Flag, unsigned &Idx) {
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if ((Flag & 0x80000000) == 0)
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return false;
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Idx = (Flag & ~0x80000000) >> 16;
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return true;
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}
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@ -477,8 +477,8 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
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assert(interval.containsOneValue());
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unsigned DefIndex = getDefIndex(interval.getValNumInfo(0)->def);
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unsigned RedefIndex = getDefIndex(MIIdx);
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// It cannot be an early clobber MO.
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assert(!MO.isEarlyClobber() && "Unexpected early clobber!");
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if (MO.isEarlyClobber())
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RedefIndex = getUseIndex(MIIdx);
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const LiveRange *OldLR = interval.getLiveRangeContaining(RedefIndex-1);
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VNInfo *OldValNo = OldLR->valno;
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@ -499,6 +499,8 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
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// Value#0 is now defined by the 2-addr instruction.
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OldValNo->def = RedefIndex;
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OldValNo->copy = 0;
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if (MO.isEarlyClobber())
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OldValNo->redefByEC = true;
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// Add the new live interval which replaces the range for the input copy.
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LiveRange LR(DefIndex, RedefIndex, ValNo);
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@ -546,8 +548,8 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
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// live until the end of the block. We've already taken care of the
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// rest of the live range.
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unsigned defIndex = getDefIndex(MIIdx);
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// It cannot be an early clobber MO.
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assert(!MO.isEarlyClobber() && "Unexpected early clobber!");
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if (MO.isEarlyClobber())
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defIndex = getUseIndex(MIIdx);
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VNInfo *ValNo;
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MachineInstr *CopyMI = NULL;
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@ -11,8 +11,9 @@
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Constants.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/Constants.h"
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#include "llvm/InlineAsm.h"
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#include "llvm/Value.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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@ -692,6 +693,35 @@ int MachineInstr::findFirstPredOperandIdx() const {
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/// isRegReDefinedByTwoAddr - Given the index of a register operand,
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/// check if the register def is a re-definition due to two addr elimination.
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bool MachineInstr::isRegReDefinedByTwoAddr(unsigned DefIdx) const{
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if (getOpcode() == TargetInstrInfo::INLINEASM) {
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assert(DefIdx >= 2);
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const MachineOperand &MO = getOperand(DefIdx);
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if (!MO.isReg() || !MO.isDef())
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return false;
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// Determine the actual operand no corresponding to this index.
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unsigned DefNo = 0;
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for (unsigned i = 1, e = getNumOperands(); i < e; ) {
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const MachineOperand &FMO = getOperand(i);
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assert(FMO.isImm());
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// Skip over this def.
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i += InlineAsm::getNumOperandRegisters(FMO.getImm()) + 1;
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if (i > DefIdx)
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break;
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++DefNo;
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}
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for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
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const MachineOperand &FMO = getOperand(i);
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if (!FMO.isImm())
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continue;
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if (i+1 >= e || !getOperand(i+1).isReg() || !getOperand(i+1).isUse())
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continue;
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unsigned Idx;
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if (InlineAsm::isUseOperandTiedToDef(FMO.getImm(), Idx) &&
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Idx == DefNo)
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return true;
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}
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}
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assert(getOperand(DefIdx).isDef() && "DefIdx is not a def!");
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const TargetInstrDesc &TID = getDesc();
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for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
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@ -707,6 +737,35 @@ bool MachineInstr::isRegReDefinedByTwoAddr(unsigned DefIdx) const{
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/// is a register use and it is tied to an def operand. It also returns the def
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/// operand index by reference.
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bool MachineInstr::isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx){
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if (getOpcode() == TargetInstrInfo::INLINEASM) {
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const MachineOperand &MO = getOperand(UseOpIdx);
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if (!MO.isReg() || !MO.isUse())
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return false;
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assert(UseOpIdx > 0);
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const MachineOperand &UFMO = getOperand(UseOpIdx-1);
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if (!UFMO.isImm())
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return false; // Must be physreg uses.
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unsigned DefNo;
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if (InlineAsm::isUseOperandTiedToDef(UFMO.getImm(), DefNo)) {
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if (!DefOpIdx)
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return true;
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unsigned DefIdx = 1;
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// Remember to adjust the index. First operand is asm string, then there
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// is a flag for each.
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while (DefNo) {
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const MachineOperand &FMO = getOperand(DefIdx);
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assert(FMO.isImm());
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// Skip over this def.
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DefIdx += InlineAsm::getNumOperandRegisters(FMO.getImm()) + 1;
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--DefNo;
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}
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*DefOpIdx = DefIdx+1;
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return true;
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}
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return false;
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}
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const TargetInstrDesc &TID = getDesc();
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if (UseOpIdx >= TID.getNumOperands())
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return false;
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@ -4932,28 +4932,17 @@ GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
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std::vector<unsigned> RegClassRegs;
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const TargetRegisterClass *RC = PhysReg.second;
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if (RC) {
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// If this is a tied register, our regalloc doesn't know how to maintain
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// the constraint, so we have to pick a register to pin the input/output to.
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// If it isn't a matched constraint, go ahead and create vreg and let the
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// regalloc do its thing.
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if (!OpInfo.hasMatchingInput()) {
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RegVT = *PhysReg.second->vt_begin();
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if (OpInfo.ConstraintVT == MVT::Other)
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ValueVT = RegVT;
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RegVT = *PhysReg.second->vt_begin();
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if (OpInfo.ConstraintVT == MVT::Other)
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ValueVT = RegVT;
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// Create the appropriate number of virtual registers.
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MachineRegisterInfo &RegInfo = MF.getRegInfo();
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for (; NumRegs; --NumRegs)
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Regs.push_back(RegInfo.createVirtualRegister(PhysReg.second));
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OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
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return;
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}
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// Otherwise, we can't allocate it. Let the code below figure out how to
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// maintain these constraints.
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RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end());
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// Create the appropriate number of virtual registers.
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MachineRegisterInfo &RegInfo = MF.getRegInfo();
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for (; NumRegs; --NumRegs)
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Regs.push_back(RegInfo.createVirtualRegister(PhysReg.second));
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OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
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return;
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} else {
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// This is a reference to a register class that doesn't directly correspond
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// to an LLVM register class. Allocate NumRegs consecutive, available,
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@ -5237,8 +5226,8 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
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OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
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6 /* EARLYCLOBBER REGDEF */ :
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2 /* REGDEF */ ,
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OpInfo.hasMatchingInput(),
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OpInfo.MatchingInput,
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false,
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0,
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DAG, AsmNodeOperands);
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break;
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}
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@ -5272,18 +5261,19 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
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RegsForValue MatchedRegs;
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MatchedRegs.TLI = &TLI;
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MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
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MatchedRegs.RegVTs.push_back(AsmNodeOperands[CurOp+1].getValueType());
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MVT RegVT = AsmNodeOperands[CurOp+1].getValueType();
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MatchedRegs.RegVTs.push_back(RegVT);
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MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
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for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
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i != e; ++i) {
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unsigned Reg =
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cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
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MatchedRegs.Regs.push_back(Reg);
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}
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i != e; ++i)
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MatchedRegs.Regs.
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push_back(RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)));
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// Use the produced MatchedRegs object to
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MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
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Chain, &Flag);
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MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, false, 0,
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MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/,
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true, OpInfo.getMatchedOperand(),
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DAG, AsmNodeOperands);
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break;
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} else {
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@ -5291,6 +5281,8 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
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assert((InlineAsm::getNumOperandRegisters(OpFlag)) == 1 &&
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"Unexpected number of operands");
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// Add information to the INLINEASM node to know about this input.
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// See InlineAsm.h isUseOperandTiedToDef.
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OpFlag |= 0x80000000 | (OpInfo.getMatchedOperand() << 16);
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AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
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TLI.getPointerTy()));
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AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
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@ -634,7 +634,9 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
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ProcessCopy(&*mi, &*mbbi, Processed);
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for (unsigned si = 1, e = TID.getNumOperands(); si < e; ++si) {
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unsigned NumOps = (mi->getOpcode() == TargetInstrInfo::INLINEASM)
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? mi->getNumOperands() : TID.getNumOperands();
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for (unsigned si = 0; si < NumOps; ++si) {
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unsigned ti = 0;
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if (!mi->isRegTiedToDefOperand(si, &ti))
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continue;
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@ -660,8 +662,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
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unsigned regA = mi->getOperand(ti).getReg();
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unsigned regB = mi->getOperand(si).getReg();
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assert(TargetRegisterInfo::isVirtualRegister(regA) &&
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TargetRegisterInfo::isVirtualRegister(regB) &&
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assert(TargetRegisterInfo::isVirtualRegister(regB) &&
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"cannot update physical register live information");
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#ifndef NDEBUG
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@ -753,7 +754,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
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}
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InstructionRearranged:
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const TargetRegisterClass* rc = MRI->getRegClass(regA);
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const TargetRegisterClass* rc = MRI->getRegClass(regB);
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MachineInstr *DefMI = MRI->getVRegDef(regB);
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// If it's safe and profitable, remat the definition instead of
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// copying it.
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@ -1017,9 +1017,37 @@ void FPS::handleSpecialFP(MachineBasicBlock::iterator &I) {
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case X86::MOV_Fp8032:
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case X86::MOV_Fp8064:
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case X86::MOV_Fp8080: {
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unsigned SrcReg = getFPReg(MI->getOperand(1));
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unsigned DestReg = getFPReg(MI->getOperand(0));
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const MachineOperand &MO1 = MI->getOperand(1);
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unsigned SrcReg = getFPReg(MO1);
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const MachineOperand &MO0 = MI->getOperand(0);
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// These can be created due to inline asm. Two address pass can introduce
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// copies from RFP registers to virtual registers.
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if (MO0.getReg() == X86::ST0 && SrcReg == 0) {
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assert(MO1.isKill());
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// Treat %ST0<def> = MOV_Fp8080 %FP0<kill>
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// like FpSET_ST0_80 %FP0<kill>, %ST0<imp-def>
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assert((StackTop == 1 || StackTop == 2)
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&& "Stack should have one or two element on it to return!");
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--StackTop; // "Forget" we have something on the top of stack!
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break;
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} else if (MO0.getReg() == X86::ST1 && SrcReg == 1) {
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assert(MO1.isKill());
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// Treat %ST1<def> = MOV_Fp8080 %FP1<kill>
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// like FpSET_ST1_80 %FP0<kill>, %ST1<imp-def>
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// StackTop can be 1 if a FpSET_ST0_* was before this. Exchange them.
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if (StackTop == 1) {
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BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(X86::ST1);
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NumFXCH++;
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StackTop = 0;
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break;
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}
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assert(StackTop == 2 && "Stack should have two element on it to return!");
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--StackTop; // "Forget" we have something on the top of stack!
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break;
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}
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unsigned DestReg = getFPReg(MO0);
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if (MI->killsRegister(X86::FP0+SrcReg)) {
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// If the input operand is killed, we can just change the owner of the
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// incoming stack slot into the result.
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@ -1,5 +1,5 @@
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; RUN: llvm-as < %s | llc | grep {a: %ecx %ecx}
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; RUN: llvm-as < %s | llc | grep {b: %ecx %edx %ecx}
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; RUN: llvm-as < %s | llc | grep {a:} | not grep ax
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; RUN: llvm-as < %s | llc | grep {b:} | not grep ax
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; PR2078
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; The clobber list says that "ax" is clobbered. Make sure that eax isn't
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; allocated to the input/output register.
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@ -1,5 +1,5 @@
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; RUN: llvm-as < %s | llc -march=x86 | grep "#%ebp %eax %edx 8(%esi) %ebx (%edi)"
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; RUN: llvm-as < %s | llc -march=x86 -regalloc=local | grep "#%ecx %eax %edx 8(%edi) %ebx (%esi)"
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; RUN: llvm-as < %s | llc -march=x86 | grep "#%ebp %edi %esi 8(%edx) %eax (%ebx)"
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; RUN: llvm-as < %s | llc -march=x86 -regalloc=local | grep "#%edi %edx %ebp 8(%ebx) %eax (%esi)"
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; The 1st, 2nd, 3rd and 5th registers above must all be different. The registers
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; referenced in the 4th and 6th operands must not be the same as the 1st or 5th
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; operand. There are many combinations that work; this is what llc puts out now.
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@ -1,5 +1,6 @@
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; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin | %prcontext End 1 | grep {movl.*%ecx}
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; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin | %prcontext End 2 | grep mov
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; PR3149
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; Make sure the copy after inline asm is not coalesced away.
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@"\01LC" = internal constant [7 x i8] c"n0=%d\0A\00" ; <[7 x i8]*> [#uses=1]
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@llvm.used = appending global [1 x i8*] [ i8* bitcast (i32 (i64, i64)* @umoddi3 to i8*) ], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0]
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9
test/CodeGen/X86/inline-asm-2addr.ll
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9
test/CodeGen/X86/inline-asm-2addr.ll
Normal file
@ -0,0 +1,9 @@
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; RUN: llvm-as < %s | llc -march=x86-64 | grep movq | count 1
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define i64 @t(i64 %a, i64 %b) nounwind ssp {
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entry:
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%asmtmp = tail call i64 asm "rorq $1,$0", "=r,J,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i64 %a) nounwind ; <i64> [#uses=1]
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%asmtmp1 = tail call i64 asm "rorq $1,$0", "=r,J,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i64 %b) nounwind ; <i64> [#uses=1]
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%0 = add i64 %asmtmp1, %asmtmp ; <i64> [#uses=1]
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ret i64 %0
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}
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