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[Hexagon] Adding A2_or instruction with IR selection pattern and test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222396 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1303,12 +1303,14 @@ bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const {
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case Hexagon::A2_pandfnew:
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case Hexagon::A2_pandt:
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case Hexagon::A2_pandtnew:
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case Hexagon::A2_porf:
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case Hexagon::A2_porfnew:
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case Hexagon::A2_port:
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case Hexagon::A2_portnew:
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case Hexagon::ADD_ri_cPt:
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case Hexagon::ADD_ri_cNotPt:
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case Hexagon::XOR_rr_cPt:
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case Hexagon::XOR_rr_cNotPt:
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case Hexagon::OR_rr_cPt:
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case Hexagon::OR_rr_cNotPt:
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case Hexagon::SUB_rr_cPt:
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case Hexagon::SUB_rr_cNotPt:
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case Hexagon::COMBINE_rr_cPt:
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@ -163,6 +163,7 @@ multiclass T_ALU32_3op_A2<string mnemonic, bits<3> MajOp, bits<3> MinOp,
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let isCodeGenOnly = 0 in
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defm add : T_ALU32_3op_A2<"add", 0b011, 0b000, 0, 1>;
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defm and : T_ALU32_3op_A2<"and", 0b001, 0b000, 0, 1>;
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defm or : T_ALU32_3op_A2<"or", 0b001, 0b001, 0, 1>;
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defm sub : T_ALU32_3op_A2<"sub", 0b011, 0b001, 1, 0>;
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// Pats for instruction selection.
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@ -172,6 +173,7 @@ class BinOp32_pat<SDNode Op, InstHexagon MI, ValueType ResT>
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def: BinOp32_pat<add, A2_add, i32>;
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def: BinOp32_pat<and, A2_and, i32>;
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def: BinOp32_pat<or, A2_or, i32>;
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def: BinOp32_pat<sub, A2_sub, i32>;
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multiclass ALU32_Pbase<string mnemonic, RegisterClass RC, bit isNot,
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@ -211,7 +213,6 @@ multiclass ALU32_base<string mnemonic, string CextOp, SDNode OpNode> {
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let isCommutable = 1 in {
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defm XOR_rr : ALU32_base<"xor", "XOR", xor>, ImmRegRel, PredNewRel;
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defm OR_rr : ALU32_base<"or", "OR", or>, ImmRegRel, PredNewRel;
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}
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defm SUB_rr : ALU32_base<"sub", "SUB", sub>, ImmRegRel, PredNewRel;
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10
test/MC/Hexagon/inst_or.ll
Normal file
10
test/MC/Hexagon/inst_or.ll
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@ -0,0 +1,10 @@
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;; RUN: llc -mtriple=hexagon-unknown-elf -filetype=obj %s -o - \
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;; RUN: | llvm-objdump -s - | FileCheck %s
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define i32 @foo (i32 %a, i32 %b)
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{
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%1 = or i32 %a, %b
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ret i32 %1
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}
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; CHECK: 0000 004120f1 00c09f52
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