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[XCore] Add intrinsic for EDU (event disable unconditional) instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202171 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -78,6 +78,7 @@ let TargetPrefix = "xcore" in { // All intrinsics start with "llvm.xcore.".
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def int_xcore_setev : Intrinsic<[],[llvm_anyptr_ty, llvm_ptr_ty],
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[NoCapture<0>]>;
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def int_xcore_eeu : Intrinsic<[],[llvm_anyptr_ty], [NoCapture<0>]>;
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def int_xcore_edu : Intrinsic<[],[llvm_anyptr_ty], [NoCapture<0>]>;
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def int_xcore_setclk : Intrinsic<[],[llvm_anyptr_ty, llvm_anyptr_ty],
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[NoCapture<0>, NoCapture<1>]>;
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def int_xcore_setrdy : Intrinsic<[],[llvm_anyptr_ty, llvm_anyptr_ty],
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@ -1013,7 +1013,8 @@ def SETEV_1r : _F1R<0b001111, (outs), (ins GRRegs:$a),
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def DGETREG_1r : _F1R<0b001110, (outs GRRegs:$a), (ins), "dgetreg $a", []>;
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def EDU_1r : _F1R<0b000000, (outs), (ins GRRegs:$a), "edu res[$a]", []>;
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def EDU_1r : _F1R<0b000000, (outs), (ins GRRegs:$a), "edu res[$a]",
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[(int_xcore_edu GRRegs:$a)]>;
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def EEU_1r : _F1R<0b000001, (outs), (ins GRRegs:$a),
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"eeu res[$a]",
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@ -21,6 +21,7 @@ declare void @llvm.xcore.syncr.p1i8(i8 addrspace(1)* %r)
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declare void @llvm.xcore.settw.p1i8(i8 addrspace(1)* %r, i32 %value)
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declare void @llvm.xcore.setv.p1i8(i8 addrspace(1)* %r, i8* %p)
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declare void @llvm.xcore.setev.p1i8(i8 addrspace(1)* %r, i8* %p)
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declare void @llvm.xcore.edu.p1i8(i8 addrspace(1)* %r)
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declare void @llvm.xcore.eeu.p1i8(i8 addrspace(1)* %r)
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declare void @llvm.xcore.setclk.p1i8.p1i8(i8 addrspace(1)* %a, i8 addrspace(1)* %b)
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declare void @llvm.xcore.setrdy.p1i8.p1i8(i8 addrspace(1)* %a, i8 addrspace(1)* %b)
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@ -184,6 +185,13 @@ define void @setev(i8 addrspace(1)* %r, i8* %p) {
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ret void
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}
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define void @edu(i8 addrspace(1)* %r) {
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; CHECK-LABEL: edu:
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; CHECK: edu res[r0]
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call void @llvm.xcore.edu.p1i8(i8 addrspace(1)* %r)
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ret void
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}
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define void @eeu(i8 addrspace(1)* %r) {
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; CHECK-LABEL: eeu:
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; CHECK: eeu res[r0]
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