mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-19 19:29:31 +00:00
Added functions to generate prolog and epilog code.
Use JMPLRET instead of RETURN for method returns so that git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@939 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vikram S. Adve
parent
1d86cc06dc
commit
fb36112c8d
@ -28,13 +28,6 @@
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//******************** Internal Data Declarations ************************/
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// to be used later
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struct BranchPattern {
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bool flipCondition; // should the sense of the test be reversed
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BasicBlock* targetBB; // which basic block to branch to
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MachineInstr* extraBranch; // if neither branch is fall-through, then this
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// BA must be inserted after the cond'l one
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};
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//************************* Forward Declarations ***************************/
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@ -50,46 +43,6 @@ static void SetMemOperands_Internal (MachineInstr* minstr,
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//************************ Internal Functions ******************************/
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//------------------------------------------------------------------------
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// External Function: ThisIsAChainRule
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//
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// Purpose:
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// Check if a given BURG rule is a chain rule.
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//------------------------------------------------------------------------
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extern bool
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ThisIsAChainRule(int eruleno)
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{
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switch(eruleno)
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{
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case 111: // stmt: reg
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case 113: // stmt: bool
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case 123:
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case 124:
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case 125:
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case 126:
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case 127:
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case 128:
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case 129:
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case 130:
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case 131:
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case 132:
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case 133:
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case 155:
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case 221:
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case 222:
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case 241:
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case 242:
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case 243:
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case 244:
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return true; break;
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default:
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return false; break;
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}
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}
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static inline MachineOpCode
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ChooseBprInstruction(const InstructionNode* instrNode)
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{
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@ -1026,28 +979,99 @@ CreateCopyInstructionsByType(const TargetMachine& target,
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}
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// This function is currently unused and incomplete but will be
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// used if we have a linear layout of basic blocks in LLVM code.
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// It decides which branch should fall-through, and whether an
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// extra unconditional branch is needed (when neither falls through).
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//
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void
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ChooseBranchPattern(Instruction* vmInstr, BranchPattern& brPattern)
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//******************* Externally Visible Functions *************************/
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//------------------------------------------------------------------------
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// External Function: GetInstructionsForProlog
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// External Function: GetInstructionsForEpilog
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//
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// Purpose:
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// Create prolog and epilog code for procedure entry and exit
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//------------------------------------------------------------------------
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extern unsigned
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GetInstructionsForProlog(BasicBlock* entryBB,
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TargetMachine &target,
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MachineInstr** mvec)
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{
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BranchInst* brInstr = (BranchInst*) vmInstr;
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int64_t s0=0; // used to avoid overloading ambiguity below
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brPattern.flipCondition = false;
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brPattern.targetBB = brInstr->getSuccessor(0);
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brPattern.extraBranch = NULL;
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// The second operand is the stack size. If it does not fit in the
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// immediate field, we either have to find an unused register in the
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// caller's window or move some elements to the dynamically allocated
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// area of the stack frame (just above save area and method args).
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Method* method = entryBB->getParent();
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MachineCodeForMethod& mcodeInfo = method->getMachineCode();
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unsigned int staticStackSize = mcodeInfo.getStaticStackSize();
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assert(brInstr->getNumSuccessors() > 1 &&
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"Unnecessary analysis for unconditional branch");
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assert(target.getInstrInfo().constantFitsInImmedField(SAVE, staticStackSize)
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&& "Stack size too large for immediate field of SAVE instruction. Need additional work as described in the comment above");
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assert(0 && "Fold branches in peephole optimization");
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mvec[0] = new MachineInstr(SAVE);
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mvec[0]->SetMachineOperand(0, target.getRegInfo().getStackPointer());
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mvec[0]->SetMachineOperand(1, MachineOperand::MO_SignExtendedImmed,
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staticStackSize);
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mvec[0]->SetMachineOperand(2, target.getRegInfo().getStackPointer());
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return 1;
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}
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//******************* Externally Visible Functions *************************/
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extern unsigned
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GetInstructionsForEpilog(BasicBlock* anExitBB,
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TargetMachine &target,
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MachineInstr** mvec)
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{
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int64_t s0=0; // used to avoid overloading ambiguity below
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mvec[0] = new MachineInstr(RESTORE);
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mvec[0]->SetMachineOperand(0, target.getRegInfo().getZeroRegNum());
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mvec[0]->SetMachineOperand(1, MachineOperand::MO_SignExtendedImmed, s0);
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mvec[0]->SetMachineOperand(2, target.getRegInfo().getZeroRegNum());
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return 1;
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}
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//------------------------------------------------------------------------
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// External Function: ThisIsAChainRule
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//
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// Purpose:
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// Check if a given BURG rule is a chain rule.
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//------------------------------------------------------------------------
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extern bool
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ThisIsAChainRule(int eruleno)
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{
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switch(eruleno)
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{
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case 111: // stmt: reg
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case 113: // stmt: bool
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case 123:
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case 124:
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case 125:
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case 126:
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case 127:
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case 128:
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case 129:
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case 130:
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case 131:
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case 132:
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case 133:
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case 155:
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case 221:
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case 222:
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case 241:
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case 242:
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case 243:
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case 244:
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return true; break;
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default:
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return false; break;
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}
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}
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//------------------------------------------------------------------------
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@ -1062,7 +1086,7 @@ unsigned
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GetInstructionsByRule(InstructionNode* subtreeRoot,
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int ruleForNode,
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short* nts,
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TargetMachine &target,
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TargetMachine &tgt,
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MachineInstr** mvec)
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{
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int numInstr = 1; // initialize for common case
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@ -1074,7 +1098,10 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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int64_t s0=0, s8=8; // variables holding constants to avoid
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uint64_t u0=0; // overloading ambiguities below
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mvec[0] = mvec[1] = mvec[2] = mvec[3] = NULL; // just for safety
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UltraSparc& target = (UltraSparc&) tgt;
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for (unsigned i=0; i < MAX_INSTR_PER_VMINSTR; i++)
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mvec[i] = NULL;
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//
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// Let's check for chain rules outside the switch so that we don't have
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@ -1101,25 +1128,27 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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// Mark the return-address register as a hidden virtual reg.
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// Mark the return value register as an implicit ref of
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// the machine instruction.
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{
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{ // Finally put a NOP in the delay slot.
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ReturnInst* returnInstr = (ReturnInst*) subtreeRoot->getInstruction();
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assert(returnInstr->getOpcode() == Instruction::Ret);
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Method* method = returnInstr->getParent()->getParent();
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Instruction* returnReg = new TmpInstruction(TMP_INSTRUCTION_OPCODE,
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returnInstr, NULL);
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returnInstr->getMachineInstrVec().addTempValue(returnReg);
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mvec[0] = new MachineInstr(RETURN);
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mvec[0] = new MachineInstr(JMPLRET);
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mvec[0]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
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returnReg);
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mvec[0]->SetMachineOperand(1, MachineOperand::MO_SignExtendedImmed,s8);
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mvec[0]->SetMachineOperand(2, target.getRegInfo().getZeroRegNum());
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if (returnInstr->getReturnValue() != NULL)
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mvec[0]->addImplicitRef(returnInstr->getReturnValue());
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// returnReg->addMachineInstruction(mvec[0]);
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unsigned n = numInstr++; // delay slot
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mvec[n] = new MachineInstr(NOP);
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mvec[numInstr++] = new MachineInstr(NOP); // delay slot
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break;
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}
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@ -1605,9 +1634,8 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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SetOperandsForMemInstr(mvec[0], subtreeRoot, target);
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break;
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case 57: // reg: Alloca: Implement as 2 instructions:
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// sub %sp, tmp -> %sp
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{ // add %sp, 0 -> result
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case 57: // reg: Alloca: Implement as 1 instruction:
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{ // add %fp, offsetFromFP -> result
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Instruction* instr = subtreeRoot->getInstruction();
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const PointerType* instrType = (const PointerType*) instr->getType();
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assert(instrType->isPointerType());
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@ -1615,25 +1643,24 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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target.findOptimalStorageSize(instrType->getValueType());
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assert(tsize != 0 && "Just to check when this can happen");
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// Create a temporary Value to hold the constant type-size
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ConstPoolSInt* valueForTSize = ConstPoolSInt::get(Type::IntTy, tsize);
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// Instruction 1: sub %sp, tsize -> %sp
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// tsize is always constant, but it may have to be put into a
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// register if it doesn't fit in the immediate field.
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//
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mvec[0] = new MachineInstr(SUB);
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mvec[0]->SetMachineOperand(0, /*regNum %sp=o6=r[14]*/(unsigned int)14);
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Method* method = instr->getParent()->getParent();
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MachineCodeForMethod& mcode = method->getMachineCode();
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int offsetFromFP =
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target.getFrameInfo().getFirstAutomaticVarOffsetFromFP(method)
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- (tsize + mcode.getAutomaticVarsSize());
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mcode.putLocalVarAtOffsetFromFP(instr, offsetFromFP, tsize);
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// Create a temporary Value to hold the constant offset.
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// This is needed because it may not fit in the immediate field.
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ConstPoolSInt* offsetVal=ConstPoolSInt::get(Type::IntTy, offsetFromFP);
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// Instruction 1: add %fp, offsetFromFP -> result
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mvec[0] = new MachineInstr(ADD);
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mvec[0]->SetMachineOperand(0, target.getRegInfo().getFramePointer());
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mvec[0]->SetMachineOperand(1, MachineOperand::MO_VirtualRegister,
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valueForTSize);
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mvec[0]->SetMachineOperand(2, /*regNum %sp=o6=r[14]*/(unsigned int)14);
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// Instruction 2: add %sp, 0 -> result
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numInstr++;
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mvec[1] = new MachineInstr(ADD);
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mvec[1]->SetMachineOperand(0, /*regNum %sp=o6=r[14]*/(unsigned int)14);
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mvec[1]->SetMachineOperand(1, target.getRegInfo().getZeroRegNum());
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mvec[1]->SetMachineOperand(2, MachineOperand::MO_VirtualRegister,
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offsetVal);
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mvec[0]->SetMachineOperand(2, MachineOperand::MO_VirtualRegister,
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instr);
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break;
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}
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@ -1641,7 +1668,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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case 58: // reg: Alloca(reg): Implement as 3 instructions:
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// mul num, typeSz -> tmp
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// sub %sp, tmp -> %sp
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{ // add %sp, 0 -> result
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{ // add %sp, frameSizeBelowDynamicArea -> result
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Instruction* instr = subtreeRoot->getInstruction();
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const PointerType* instrType = (const PointerType*) instr->getType();
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assert(instrType->isPointerType() &&
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@ -1649,18 +1676,26 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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const Type* eltType =
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((ArrayType*) instrType->getValueType())->getElementType();
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int tsize = (int) target.findOptimalStorageSize(eltType);
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assert(tsize != 0 && "Just to check when this can happen");
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// if (tsize == 0)
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// {
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// numInstr = 0;
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// break;
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// }
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//else go on to create the instructions needed...
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// Create a temporary Value to hold the constant type-size
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ConstPoolSInt* valueForTSize = ConstPoolSInt::get(Type::IntTy, tsize);
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ConstPoolSInt* tsizeVal = ConstPoolSInt::get(Type::IntTy, tsize);
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// Create a temporary Value to hold the constant offset from SP
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Method* method = instr->getParent()->getParent();
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MachineCodeForMethod& mcode = method->getMachineCode();
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int frameSizeBelowDynamicArea =
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target.getFrameInfo().getFrameSizeBelowDynamicArea(method);
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ConstPoolSInt* lowerAreaSizeVal = ConstPoolSInt::get(Type::IntTy,
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frameSizeBelowDynamicArea);
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cerr << "***" << endl
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<< "*** Variable-size ALLOCA operation needs more work:" << endl
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<< "*** We have to precompute the size of "
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<< " optional arguments in the stack frame" << endl
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<< "***" << endl;
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assert(0 && "SEE MESSAGE ABOVE");
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// Create a temporary value to hold `tmp'
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Instruction* tmpInstr = new TmpInstruction(TMP_INSTRUCTION_OPCODE,
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subtreeRoot->leftChild()->getValue(),
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@ -1670,34 +1705,32 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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// Instruction 1: mul numElements, typeSize -> tmp
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mvec[0] = new MachineInstr(MULX);
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mvec[0]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
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subtreeRoot->leftChild()->getValue());
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subtreeRoot->leftChild()->getValue());
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mvec[0]->SetMachineOperand(1, MachineOperand::MO_VirtualRegister,
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valueForTSize);
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tsizeVal);
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mvec[0]->SetMachineOperand(2, MachineOperand::MO_VirtualRegister,
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tmpInstr);
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// tmpInstr->addMachineInstruction(mvec[0]);
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// Instruction 2: sub %sp, tmp -> %sp
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numInstr++;
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mvec[1] = new MachineInstr(SUB);
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mvec[1]->SetMachineOperand(0, /*regNum %sp=o6=r[14]*/(unsigned int)14);
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mvec[1]->SetMachineOperand(0, target.getRegInfo().getStackPointer());
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mvec[1]->SetMachineOperand(1, MachineOperand::MO_VirtualRegister,
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tmpInstr);
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mvec[1]->SetMachineOperand(2, /*regNum %sp=o6=r[14]*/(unsigned int)14);
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mvec[1]->SetMachineOperand(2, target.getRegInfo().getStackPointer());
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// Instruction 3: add %sp, 0 -> result
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// Instruction 3: add %sp, frameSizeBelowDynamicArea -> result
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numInstr++;
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mvec[2] = new MachineInstr(ADD);
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mvec[2]->SetMachineOperand(0, /*regNum %sp=o6=r[14]*/(unsigned int)14);
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mvec[2]->SetMachineOperand(1, target.getRegInfo().getZeroRegNum());
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mvec[2]->SetMachineOperand(2, MachineOperand::MO_VirtualRegister,
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instr);
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mvec[2]->SetMachineOperand(0, target.getRegInfo().getStackPointer());
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mvec[2]->SetMachineOperand(1, MachineOperand::MO_VirtualRegister,
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lowerAreaSizeVal);
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mvec[2]->SetMachineOperand(2,MachineOperand::MO_VirtualRegister,instr);
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break;
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}
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case 61: // reg: Call
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// Generate a call-indirect (i.e., JMPL) for now to expose
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// Generate a call-indirect (i.e., jmpl) for now to expose
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// the potential need for registers. If an absolute address
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// is available, replace this with a CALL instruction.
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// Mark both the indirection register and the return-address
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@ -1733,7 +1766,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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}
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else
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{ // indirect function call
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mvec[0] = new MachineInstr(JMPL);
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mvec[0] = new MachineInstr(JMPLCALL);
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mvec[0]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
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callee);
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mvec[0]->SetMachineOperand(1, MachineOperand::MO_SignExtendedImmed,
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