6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-06-13 04:38:24 +00:00
Code Issues Projects Releases Wiki Activity

Switch most getReservedRegs() clients to the MRI equivalent.

Browse Source 
Using the cached bit vector in MRI avoids comstantly allocating and
recomputing the reserved register bit vector.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165983 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
2012-10-15 21:57:41 +00:00
parent e4f273908b
commit fb9ebbf236
12 changed files with 28 additions and 52 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
lib/CodeGen/VirtRegMap.cpp
View File

@ -257,9 +257,6 @@ void VirtRegRewriter::rewrite() {
SmallVector<unsigned, 8> SuperDeads;
SmallVector<unsigned, 8> SuperDefs;
SmallVector<unsigned, 8> SuperKills;
#ifndef NDEBUG
BitVector Reserved = TRI->getReservedRegs(*MF);
#endif
for (MachineFunction::iterator MBBI = MF->begin(), MBBE = MF->end();
MBBI != MBBE; ++MBBI) {
@ -283,7 +280,7 @@ void VirtRegRewriter::rewrite() {
unsigned PhysReg = VRM->getPhys(VirtReg);
assert(PhysReg != VirtRegMap::NO_PHYS_REG &&
"Instruction uses unmapped VirtReg");
assert(!Reserved.test(PhysReg) && "Reserved register assignment");
assert(!MRI->isReserved(PhysReg) && "Reserved register assignment");
// Preserve semantics of sub-register operands.
if (MO.getSubReg()) {