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Remove useMachineScheduler and replace it with subtarget options
that control, individually, all of the disparate things it was controlling. At the same time move a FIXME in the Hexagon port to a new subtarget function that will enable a user of the machine scheduler to avoid using the source scheduler for pre-RA-scheduling. The FIXME would have this removed, but involves either testcase changes or adding -pre-RA-sched=source to a few testcases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231980 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -94,16 +94,24 @@ public:
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return 0;
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}
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/// \brief Temporary API to test migration to MI scheduler.
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bool useMachineScheduler() const;
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/// \brief True if the subtarget should run MachineScheduler after aggressive
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/// coalescing.
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///
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/// This currently replaces the SelectionDAG scheduler with the "source" order
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/// scheduler. It does not yet disable the postRA scheduler.
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/// scheduler (though see below for an option to turn this off and use the
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/// TargetLowering preference). It does not yet disable the postRA scheduler.
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virtual bool enableMachineScheduler() const;
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/// \brief True if the machine scheduler should disable the TLI preference
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/// for preRA scheduling with the source level scheduler.
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virtual bool enableMachineSchedDefaultSched() const { return true; }
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/// \brief True if the subtarget should enable joining global copies.
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///
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/// By default this is enabled if the machine scheduler is enabled, but
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/// can be overridden.
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virtual bool enableJoinGlobalCopies() const;
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/// \brief True if the subtarget should run PostMachineScheduler.
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///
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/// This only takes effect if the target has configured the
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@ -209,6 +209,11 @@ static MachineSchedRegistry
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DefaultSchedRegistry("default", "Use the target's default scheduler choice.",
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useDefaultMachineSched);
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static cl::opt<bool> EnableMachineSched(
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"enable-misched",
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cl::desc("Enable the machine instruction scheduling pass."), cl::init(true),
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cl::Hidden);
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/// Forward declare the standard machine scheduler. This will be used as the
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/// default scheduler if the target does not set a default.
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static ScheduleDAGInstrs *createGenericSchedLive(MachineSchedContext *C);
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@ -304,6 +309,12 @@ ScheduleDAGInstrs *PostMachineScheduler::createPostMachineScheduler() {
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/// design would be to split blocks at scheduling boundaries, but LLVM has a
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/// general bias against block splitting purely for implementation simplicity.
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bool MachineScheduler::runOnMachineFunction(MachineFunction &mf) {
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if (EnableMachineSched.getNumOccurrences()) {
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if (!EnableMachineSched)
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return false;
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} else if (!mf.getSubtarget().enableMachineScheduler())
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return false;
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DEBUG(dbgs() << "Before MISsched:\n"; mf.print(dbgs()));
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// Initialize the context of the pass.
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@ -55,9 +55,6 @@ static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden,
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static cl::opt<cl::boolOrDefault>
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OptimizeRegAlloc("optimize-regalloc", cl::Hidden,
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cl::desc("Enable optimized register allocation compilation path."));
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static cl::opt<cl::boolOrDefault>
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EnableMachineSched("enable-misched",
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cl::desc("Enable the machine instruction scheduling pass."));
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static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
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cl::Hidden,
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cl::desc("Disable Machine LICM"));
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@ -116,28 +113,6 @@ static IdentifyingPassPtr applyDisable(IdentifyingPassPtr PassID,
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return PassID;
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}
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/// Allow Pass selection to be overriden by command line options. This supports
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/// flags with ternary conditions. TargetID is passed through by default. The
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/// pass is suppressed when the option is false. When the option is true, the
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/// StandardID is selected if the target provides no default.
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static IdentifyingPassPtr applyOverride(IdentifyingPassPtr TargetID,
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cl::boolOrDefault Override,
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AnalysisID StandardID) {
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switch (Override) {
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case cl::BOU_UNSET:
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return TargetID;
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case cl::BOU_TRUE:
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if (TargetID.isValid())
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return TargetID;
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if (StandardID == nullptr)
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report_fatal_error("Target cannot enable pass");
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return StandardID;
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case cl::BOU_FALSE:
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return IdentifyingPassPtr();
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}
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llvm_unreachable("Invalid command line option state");
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}
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/// Allow standard passes to be disabled by the command line, regardless of who
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/// is adding the pass.
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///
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@ -182,9 +157,6 @@ static IdentifyingPassPtr overridePass(AnalysisID StandardID,
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if (StandardID == &MachineCSEID)
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return applyDisable(TargetID, DisableMachineCSE);
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if (StandardID == &MachineSchedulerID)
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return applyOverride(TargetID, EnableMachineSched, StandardID);
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if (StandardID == &TargetPassConfig::PostRAMachineLICMID)
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return applyDisable(TargetID, DisablePostRAMachineLICM);
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@ -249,11 +221,6 @@ TargetPassConfig::TargetPassConfig(TargetMachine *tm, PassManagerBase &pm)
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// Substitute Pseudo Pass IDs for real ones.
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substitutePass(&EarlyTailDuplicateID, &TailDuplicateID);
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substitutePass(&PostRAMachineLICMID, &MachineLICMID);
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// Temporarily disable experimental passes.
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const TargetSubtargetInfo &ST = *TM->getSubtargetImpl();
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if (!ST.useMachineScheduler())
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disablePass(&MachineSchedulerID);
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}
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/// Insert InsertedPassID pass after TargetPassID.
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@ -2771,7 +2771,7 @@ bool RegisterCoalescer::runOnMachineFunction(MachineFunction &fn) {
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AA = &getAnalysis<AliasAnalysis>();
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Loops = &getAnalysis<MachineLoopInfo>();
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if (EnableGlobalCopies == cl::BOU_UNSET)
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JoinGlobalCopies = STI.useMachineScheduler();
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JoinGlobalCopies = STI.enableJoinGlobalCopies();
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else
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JoinGlobalCopies = (EnableGlobalCopies == cl::BOU_TRUE);
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@ -292,7 +292,8 @@ namespace llvm {
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const TargetLowering *TLI = IS->TLI;
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const TargetSubtargetInfo &ST = IS->MF->getSubtarget();
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if (OptLevel == CodeGenOpt::None || ST.useMachineScheduler() ||
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if (OptLevel == CodeGenOpt::None ||
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(ST.enableMachineScheduler() && ST.enableMachineSchedDefaultSched()) ||
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TLI->getSchedulingPreference() == Sched::Source)
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return createSourceListDAGScheduler(IS, OptLevel);
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if (TLI->getSchedulingPreference() == Sched::RegPressure)
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@ -48,6 +48,10 @@ EnableIEEERndNear(
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cl::Hidden, cl::ZeroOrMore, cl::init(false),
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cl::desc("Generate non-chopped conversion from fp to int."));
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static cl::opt<bool> DisableHexagonMISched("disable-hexagon-misched",
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cl::Hidden, cl::ZeroOrMore, cl::init(false),
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cl::desc("Disable Hexagon MI Scheduling"));
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HexagonSubtarget &
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HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
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// If the programmer has not specified a Hexagon version, default to -mv4.
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@ -91,3 +95,9 @@ HexagonSubtarget::HexagonSubtarget(StringRef TT, StringRef CPU, StringRef FS,
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// Pin the vtable to this file.
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void HexagonSubtarget::anchor() {}
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bool HexagonSubtarget::enableMachineScheduler() const {
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if (DisableHexagonMISched.getNumOccurrences())
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return !DisableHexagonMISched;
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return true;
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}
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@ -85,6 +85,11 @@ public:
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bool hasV5TOps() const { return getHexagonArchVersion() >= V5; }
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bool hasV5TOpsOnly() const { return getHexagonArchVersion() == V5; }
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bool modeIEEERndNear() const { return ModeIEEERndNear; }
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bool enableMachineScheduler() const override;
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// Always use the TargetLowering default scheduler.
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// FIXME: This will use the vliw scheduler which is probably just hurting
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// compiler time and will be removed eventually anyway.
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bool enableMachineSchedDefaultSched() const override { return false; }
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const std::string &getCPUString () const { return CPUString; }
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@ -29,10 +29,6 @@ using namespace llvm;
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static cl:: opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
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cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
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static cl::opt<bool> DisableHexagonMISched("disable-hexagon-misched",
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cl::Hidden, cl::ZeroOrMore, cl::init(false),
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cl::desc("Disable Hexagon MI Scheduling"));
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static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
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cl::Hidden, cl::ZeroOrMore, cl::init(false),
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cl::desc("Disable Hexagon CFG Optimization"));
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@ -82,16 +78,7 @@ namespace {
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class HexagonPassConfig : public TargetPassConfig {
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public:
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HexagonPassConfig(HexagonTargetMachine *TM, PassManagerBase &PM)
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: TargetPassConfig(TM, PM) {
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// FIXME: Rather than calling enablePass(&MachineSchedulerID) below, define
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// HexagonSubtarget::enableMachineScheduler() { return true; }.
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// That will bypass the SelectionDAG VLIW scheduler, which is probably just
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// hurting compile time and will be removed eventually anyway.
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if (DisableHexagonMISched)
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disablePass(&MachineSchedulerID);
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else
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enablePass(&MachineSchedulerID);
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}
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: TargetPassConfig(TM, PM) {}
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HexagonTargetMachine &getHexagonTargetMachine() const {
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return getTM<HexagonTargetMachine>();
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@ -23,22 +23,6 @@ TargetSubtargetInfo::TargetSubtargetInfo() {}
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TargetSubtargetInfo::~TargetSubtargetInfo() {}
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// Temporary option to compare overall performance change when moving from the
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// SD scheduler to the MachineScheduler pass pipeline. This is convenient for
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// benchmarking during the transition from SD to MI scheduling. Once armv7 makes
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// the switch, it should go away. The normal way to enable/disable the
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// MachineScheduling pass itself is by using -enable-misched. For targets that
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// already use MI sched (via MySubTarget::enableMachineScheduler())
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// -misched-bench=false negates the subtarget hook.
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static cl::opt<bool> BenchMachineSched("misched-bench", cl::Hidden,
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cl::desc("Migrate from the target's default SD scheduler to MI scheduler"));
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bool TargetSubtargetInfo::useMachineScheduler() const {
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if (BenchMachineSched.getNumOccurrences())
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return BenchMachineSched;
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return enableMachineScheduler();
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}
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bool TargetSubtargetInfo::enableAtomicExpand() const {
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return true;
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}
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@ -47,6 +31,10 @@ bool TargetSubtargetInfo::enableMachineScheduler() const {
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return false;
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}
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bool TargetSubtargetInfo::enableJoinGlobalCopies() const {
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return enableMachineScheduler();
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}
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bool TargetSubtargetInfo::enableRALocalReassignment(
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CodeGenOpt::Level OptLevel) const {
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return true;
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