mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-14 11:32:34 +00:00
CR fixes per Bruno's request.
Undo the changes from r139285 which added custom lowering to vselect. Add tablegen lowering for vselect. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139479 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nadav Rotem
parent
cfeb55cdbc
commit
fbad25e120
@ -149,6 +149,10 @@ def SDTSelect : SDTypeProfile<1, 3, [ // select
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SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>
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]>;
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def SDTVSelect : SDTypeProfile<1, 3, [ // vselect
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SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>
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]>;
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def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc
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SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>,
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SDTCisVT<5, OtherVT>
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@ -390,8 +394,8 @@ def f32_to_f16 : SDNode<"ISD::FP32_TO_FP16", SDTFPToIntOp>;
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def setcc : SDNode<"ISD::SETCC" , SDTSetCC>;
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def select : SDNode<"ISD::SELECT" , SDTSelect>;
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def vselect : SDNode<"ISD::VSELECT" , SDTVSelect>;
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def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>;
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def vsetcc : SDNode<"ISD::VSETCC" , SDTSetCC>;
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def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>;
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def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>;
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@ -917,11 +917,11 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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setOperationAction(ISD::SHL, MVT::v4i32, Custom);
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setOperationAction(ISD::SHL, MVT::v16i8, Custom);
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setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
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setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
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setOperationAction(ISD::VSELECT, MVT::v16i8, Custom);
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setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
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setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
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setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
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setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
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setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
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setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
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setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
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// i8 and i16 vectors are custom , because the source register and source
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// source memory operand types are not the same width. f32 vectors are
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@ -1019,10 +1019,10 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
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setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
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setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
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setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
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setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
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setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
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setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
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setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
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setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
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setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
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setOperationAction(ISD::ADD, MVT::v4i64, Custom);
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setOperationAction(ISD::ADD, MVT::v8i32, Custom);
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@ -8703,43 +8703,6 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
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return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
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}
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SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
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SDValue Cond = Op.getOperand(0);
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SDValue Op1 = Op.getOperand(1);
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SDValue Op2 = Op.getOperand(2);
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DebugLoc DL = Op.getDebugLoc();
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SDValue Ops[] = {Op1, Op2, Cond};
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assert(Op1.getValueType().isVector() && "Op1 must be a vector");
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assert(Op2.getValueType().isVector() && "Op2 must be a vector");
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assert(Cond.getValueType().isVector() && "Cond must be a vector");
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assert(Op1.getValueType() == Op2.getValueType() && "Type mismatch");
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EVT VT = Op1.getValueType();
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switch (VT.getSimpleVT().SimpleTy) {
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default: break;
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// SSE4:
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case MVT::v2i64:
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case MVT::v2f64:
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case MVT::v4i32:
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case MVT::v4f32:
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case MVT::v16i8:
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case MVT::v8i16:
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// AVX:
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case MVT::v4i64:
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case MVT::v4f64:
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case MVT::v8i32:
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case MVT::v8f32:
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case MVT::v32i8:
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case MVT::v16i16:
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return DAG.getNode(X86ISD::BLENDV, DL, VT, Ops, array_lengthof(Ops));
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}
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return SDValue();
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}
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// isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
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// ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
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// from the AND / OR.
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@ -9993,7 +9956,7 @@ SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
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M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
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DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
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DAG.getConstant(4, MVT::i32));
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R = DAG.getNode(X86ISD::BLENDV, dl, VT, R, M, Op);
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R = DAG.getNode(ISD::VSELECT, dl, VT, Op, R, M);
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// a += a
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Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
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@ -10008,13 +9971,13 @@ SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
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M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
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DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
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DAG.getConstant(2, MVT::i32));
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R = DAG.getNode(X86ISD::BLENDV, dl, VT, R, M, Op);
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R = DAG.getNode(ISD::VSELECT, dl, VT, Op, R, M);
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// a += a
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Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
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// return pblendv(r, r+r, a);
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R = DAG.getNode(X86ISD::BLENDV, dl, VT,
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R, DAG.getNode(ISD::ADD, dl, VT, R, R), Op);
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R = DAG.getNode(ISD::VSELECT, dl, VT, Op,
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R, DAG.getNode(ISD::ADD, dl, VT, R, R));
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return R;
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}
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return SDValue();
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@ -10406,7 +10369,6 @@ SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
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case ISD::SETCC: return LowerSETCC(Op, DAG);
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case ISD::SELECT: return LowerSELECT(Op, DAG);
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case ISD::VSELECT: return LowerVSELECT(Op, DAG);
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case ISD::BRCOND: return LowerBRCOND(Op, DAG);
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case ISD::JumpTable: return LowerJumpTable(Op, DAG);
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case ISD::VASTART: return LowerVASTART(Op, DAG);
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@ -10651,7 +10613,6 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::PSIGNB: return "X86ISD::PSIGNB";
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case X86ISD::PSIGNW: return "X86ISD::PSIGNW";
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case X86ISD::PSIGND: return "X86ISD::PSIGND";
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case X86ISD::BLENDV: return "X86ISD::BLENDV";
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case X86ISD::FMAX: return "X86ISD::FMAX";
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case X86ISD::FMIN: return "X86ISD::FMIN";
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case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
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@ -13381,7 +13342,7 @@ static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
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X = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, X);
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Y = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Y);
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Mask = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Mask);
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Mask = DAG.getNode(X86ISD::BLENDV, DL, MVT::v16i8, X, Y, Mask);
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Mask = DAG.getNode(ISD::VSELECT, DL, MVT::v16i8, Mask, X, Y);
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return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Mask);
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}
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}
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@ -809,7 +809,6 @@ namespace llvm {
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SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
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@ -5869,36 +5869,27 @@ defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, i256mem,
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let Predicates = [HasAVX] in {
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def : Pat<(v16i8 (X86blendv (v16i8 VR128:$src1), (v16i8 VR128:$src2),
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VR128:$mask)),
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(VPBLENDVBrr VR128:$src1, VR128:$src2, VR128:$mask)>;
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def : Pat<(v4i32 (X86blendv (v4i32 VR128:$src1), (v4i32 VR128:$src2),
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VR128:$mask)),
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(VBLENDVPSrr VR128:$src1, VR128:$src2, VR128:$mask)>;
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def : Pat<(v4f32 (X86blendv (v4f32 VR128:$src1), (v4f32 VR128:$src2),
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VR128:$mask)),
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(VBLENDVPSrr VR128:$src1, VR128:$src2, VR128:$mask)>;
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def : Pat<(v2i64 (X86blendv (v2i64 VR128:$src1), (v2i64 VR128:$src2),
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VR128:$mask)),
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(VBLENDVPDrr VR128:$src1, VR128:$src2, VR128:$mask)>;
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def : Pat<(v2f64 (X86blendv (v2f64 VR128:$src1), (v2f64 VR128:$src2),
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VR128:$mask)),
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(VBLENDVPDrr VR128:$src1, VR128:$src2, VR128:$mask)>;
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VR128:$mask)), (VPBLENDVBrr VR128:$src1, VR128:$src2, VR128:$mask)>;
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def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
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(v16i8 VR128:$src2))), (VPBLENDVBrr VR128:$src1, VR128:$src2, VR128:$mask)>;
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def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
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(v4i32 VR128:$src2))), (VBLENDVPSrr VR128:$src1, VR128:$src2, VR128:$mask)>;
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def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
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(v4f32 VR128:$src2))), (VBLENDVPSrr VR128:$src1, VR128:$src2, VR128:$mask)>;
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def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
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(v2i64 VR128:$src2))), (VBLENDVPDrr VR128:$src1, VR128:$src2, VR128:$mask)>;
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def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
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(v2f64 VR128:$src2))), (VBLENDVPDrr VR128:$src1, VR128:$src2, VR128:$mask)>;
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def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
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(v8i32 VR256:$src2))), (VBLENDVPSYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
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def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
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(v8f32 VR256:$src2))), (VBLENDVPSYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
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def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
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(v4i64 VR256:$src2))), (VBLENDVPDYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
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def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
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(v4f64 VR256:$src2))), (VBLENDVPDYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
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def : Pat<(v8i32 (X86blendv (v8i32 VR256:$src1), (v8i32 VR256:$src2),
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VR256:$mask)),
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(VBLENDVPSYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
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def : Pat<(v8f32 (X86blendv (v8f32 VR256:$src1), (v8f32 VR256:$src2),
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VR256:$mask)),
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(VBLENDVPSYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
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def : Pat<(v4i64 (X86blendv (v4i64 VR256:$src1), (v4i64 VR256:$src2),
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VR256:$mask)),
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(VBLENDVPDYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
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def : Pat<(v4f64 (X86blendv (v4f64 VR256:$src1), (v4f64 VR256:$src2),
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VR256:$mask)),
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(VBLENDVPDYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
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}
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/// SS41I_ternary_int - SSE 4.1 ternary operator
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@ -5926,16 +5917,19 @@ defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
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defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
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let Predicates = [HasSSE41] in {
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def : Pat<(v16i8 (X86blendv (v16i8 VR128:$src1), (v16i8 VR128:$src2), XMM0)),
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(PBLENDVBrr0 VR128:$src1, VR128:$src2)>;
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def : Pat<(v4i32 (X86blendv (v4i32 VR128:$src1), (v4i32 VR128:$src2), XMM0)),
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(BLENDVPSrr0 VR128:$src1, VR128:$src2)>;
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def : Pat<(v4f32 (X86blendv (v4f32 VR128:$src1), (v4f32 VR128:$src2), XMM0)),
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(BLENDVPSrr0 VR128:$src1, VR128:$src2)>;
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def : Pat<(v2i64 (X86blendv (v2i64 VR128:$src1), (v2i64 VR128:$src2), XMM0)),
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(BLENDVPDrr0 VR128:$src1, VR128:$src2)>;
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def : Pat<(v2f64 (X86blendv (v2f64 VR128:$src1), (v2f64 VR128:$src2), XMM0)),
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(BLENDVPDrr0 VR128:$src1, VR128:$src2)>;
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def : Pat<(v16i8 (X86blendv (v16i8 VR128:$src1), (v16i8 VR128:$src2),
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VR128:$mask)), (VPBLENDVBrr VR128:$src1, VR128:$src2, VR128:$mask)>;
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def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
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(v16i8 VR128:$src2))), (PBLENDVBrr0 VR128:$src1, VR128:$src2)>;
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def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
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(v4i32 VR128:$src2))), (BLENDVPSrr0 VR128:$src1, VR128:$src2)>;
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def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
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(v4f32 VR128:$src2))), (BLENDVPSrr0 VR128:$src1, VR128:$src2)>;
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def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
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(v2i64 VR128:$src2))), (BLENDVPDrr0 VR128:$src1, VR128:$src2)>;
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def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
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(v2f64 VR128:$src2))), (BLENDVPDrr0 VR128:$src1, VR128:$src2)>;
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}
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let Predicates = [HasAVX] in
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