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AArch64: fall back to generic code for out of range extract/insert.

Browse Source 
rdar://problem/17624784

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213059 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover 2014-07-15 10:00:26 +00:00
parent 218f127b63
commit fbb631183a
2 changed files with 25 additions and 6 deletions
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14
lib/Target/AArch64/AArch64ISelLowering.cpp
View File

@ -5584,11 +5584,12 @@ SDValue AArch64TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
SelectionDAG &DAG) const { SelectionDAG &DAG) const {
assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT && "Unknown opcode!"); assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT && "Unknown opcode!");
// Check for non-constant lane. // Check for non-constant or out of range lane.
if (!isa<ConstantSDNode>(Op.getOperand(2))) EVT VT = Op.getOperand(0).getValueType();
ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Op.getOperand(2));
if (!CI || CI->getZExtValue() >= VT.getVectorNumElements())
return SDValue(); return SDValue();
EVT VT = Op.getOperand(0).getValueType();
// Insertion/extraction are legal for V128 types. // Insertion/extraction are legal for V128 types.
if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 || if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
@ -5616,11 +5617,12 @@ AArch64TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
SelectionDAG &DAG) const { SelectionDAG &DAG) const {
assert(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && "Unknown opcode!"); assert(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && "Unknown opcode!");
// Check for non-constant lane. // Check for non-constant or out of range lane.
if (!isa<ConstantSDNode>(Op.getOperand(1))) EVT VT = Op.getOperand(0).getValueType();
ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Op.getOperand(1));
if (!CI || CI->getZExtValue() >= VT.getVectorNumElements())
return SDValue(); return SDValue();
EVT VT = Op.getOperand(0).getValueType();
// Insertion/extraction are legal for V128 types. // Insertion/extraction are legal for V128 types.
if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 || if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||

17
test/CodeGen/AArch64/neon-scalar-copy.ll
View File

@ -101,3 +101,20 @@ define <1 x i64> @test_vector_copy_dup_dv2D(<1 x i64> %a, <2 x i64> %c) {
ret <1 x i64> %vset_lane ret <1 x i64> %vset_lane
} }
; Undefined behaviour, so we really don't care what actually gets emitted, just
; as long as we don't crash (since it could be dynamically unreachable).
define i32 @test_out_of_range_extract(<4 x i32> %vec) {
; CHECK-LABEL: test_out_of_range_extract:
; CHECK: ret
%elt = extractelement <4 x i32> %vec, i32 4
ret i32 %elt
}
; Undefined behaviour, so we really don't care what actually gets emitted, just
; as long as we don't crash (since it could be dynamically unreachable).
define void @test_out_of_range_insert(<4 x i32> %vec, i32 %elt) {
; CHECK-LABEL: test_out_of_range_insert:
; CHECK: ret
insertelement <4 x i32> %vec, i32 %elt, i32 4
ret void
}