6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-09-30 04:56:49 +00:00
Code Issues Projects Releases Wiki Activity

ARM: 'add Rd, pc, #imm' is an alias for 'adr Rd, #imm'.

Browse Source 
rdar://9795790

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164577 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2012-09-25 00:08:13 +00:00
parent 1afd6bb939
commit fbc21fabae
2 changed files with 18 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -5666,6 +5666,20 @@ bool ARMAsmParser::
processInstruction(MCInst &Inst,
const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
switch (Inst.getOpcode()) {
// Alias for alternate form of 'ADR Rd, #imm' instruction.
case ARM::ADDri: {
if (Inst.getOperand(1).getReg() != ARM::PC ||
Inst.getOperand(5).getReg() != 0)
return false;
MCInst TmpInst;
TmpInst.setOpcode(ARM::ADR);
TmpInst.addOperand(Inst.getOperand(0));
TmpInst.addOperand(Inst.getOperand(2));
TmpInst.addOperand(Inst.getOperand(3));
TmpInst.addOperand(Inst.getOperand(4));
Inst = TmpInst;
return true;
}
// Aliases for alternate PC+imm syntax of LDR instructions.
case ARM::t2LDRpcrel:
Inst.setOpcode(ARM::t2LDRpci);

4
test/MC/ARM/arm-arithmetic-aliases.s
View File

@ -124,3 +124,7 @@ bicseq r2, r3
@ CHECK: bicseq r2, r2, #6 @ encoding: [0x06,0x20,0xd2,0x03]
@ CHECK: bicseq r2, r2, r3 @ encoding: [0x03,0x20,0xd2,0x01]
@ CHECK: bicseq r2, r2, r3 @ encoding: [0x03,0x20,0xd2,0x01]
add r0, pc, #123
@ CHECK: adr r0, #123 @ encoding: [0x7b,0x00,0x8f,0xe2]