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[mips] [IAS] Give expandLoadAddressSym() more specific arguments. NFC.

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Summary:
If we only pass the necessary operands, we don't have to determine the position of the symbol operand when entering expandLoadAddressSym().
This simplifies the expandLoadAddressSym() code.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9291

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237355 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Toma Tabacu 2015-05-14 10:02:58 +00:00
parent 3f7bd961d1
commit fbcecce27e
1 changed files with 13 additions and 23 deletions
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36
lib/Target/Mips/AsmParser/MipsAsmParser.cpp
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@ -194,8 +194,8 @@ class MipsAsmParser : public MCTargetAsmParser {
bool expandUncondBranchMMPseudo(MCInst &Inst, SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions);
void expandLoadAddressSym(MCInst &Inst, SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions);
void expandLoadAddressSym(const MCOperand &DstRegOp, const MCOperand &SymOp,
SMLoc IDLoc, SmallVectorImpl<MCInst> &Instructions);
void expandMemInst(MCInst &Inst, SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions, bool isLoad,
@ -1869,17 +1869,18 @@ bool MipsAsmParser::expandLoadImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc,
bool
MipsAsmParser::expandLoadAddressReg(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions) {
const MCOperand &DstRegOp = Inst.getOperand(0);
assert(DstRegOp.isReg() && "expected register operand kind");
const MCOperand &ImmOp = Inst.getOperand(2);
assert((ImmOp.isImm() || ImmOp.isExpr()) &&
"expected immediate operand kind");
if (!ImmOp.isImm()) {
expandLoadAddressSym(Inst, IDLoc, Instructions);
expandLoadAddressSym(DstRegOp, ImmOp, IDLoc, Instructions);
return false;
}
const MCOperand &SrcRegOp = Inst.getOperand(1);
assert(SrcRegOp.isReg() && "expected register operand kind");
const MCOperand &DstRegOp = Inst.getOperand(0);
assert(DstRegOp.isReg() && "expected register operand kind");
if (loadImmediate(ImmOp.getImm(), DstRegOp.getReg(), SrcRegOp.getReg(),
Is32BitImm, IDLoc, Instructions))
@ -1891,15 +1892,16 @@ MipsAsmParser::expandLoadAddressReg(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc,
bool
MipsAsmParser::expandLoadAddressImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions) {
const MCOperand &DstRegOp = Inst.getOperand(0);
assert(DstRegOp.isReg() && "expected register operand kind");
const MCOperand &ImmOp = Inst.getOperand(1);
assert((ImmOp.isImm() || ImmOp.isExpr()) &&
"expected immediate operand kind");
if (!ImmOp.isImm()) {
expandLoadAddressSym(Inst, IDLoc, Instructions);
expandLoadAddressSym(DstRegOp, ImmOp, IDLoc, Instructions);
return false;
}
const MCOperand &DstRegOp = Inst.getOperand(0);
assert(DstRegOp.isReg() && "expected register operand kind");
if (loadImmediate(ImmOp.getImm(), DstRegOp.getReg(), Mips::NoRegister,
Is32BitImm, IDLoc, Instructions))
@ -1909,23 +1911,11 @@ MipsAsmParser::expandLoadAddressImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc,
}
void
MipsAsmParser::expandLoadAddressSym(MCInst &Inst, SMLoc IDLoc,
MipsAsmParser::expandLoadAddressSym(const MCOperand &DstRegOp,
const MCOperand &SymOp, SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions) {
// FIXME: If we do have a valid at register to use, we should generate a
// slightly shorter sequence here.
MCInst tmpInst;
int ExprOperandNo = 1;
// Sometimes the assembly parser will get the immediate expression as
// a $zero + an immediate.
if (Inst.getNumOperands() == 3) {
assert(Inst.getOperand(1).getReg() ==
(isGP64bit() ? Mips::ZERO_64 : Mips::ZERO));
ExprOperandNo = 2;
}
const MCOperand &SymOp = Inst.getOperand(ExprOperandNo);
assert(SymOp.isExpr() && "expected symbol operand kind");
const MCOperand &RegOp = Inst.getOperand(0);
unsigned RegNo = RegOp.getReg();
unsigned RegNo = DstRegOp.getReg();
const MCSymbolRefExpr *Symbol = cast<MCSymbolRefExpr>(SymOp.getExpr());
const MCSymbolRefExpr *HiExpr =
MCSymbolRefExpr::Create(Symbol->getSymbol().getName(),