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Merged from r221604:
[mips] Fix sret arguments for N32/N64 which were accidentally broken in r221534. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_35@223070 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -128,6 +128,7 @@ void MipsCCState::PreAnalyzeFormalArgumentsForF128(
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// aren't mapped to an original argument.
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if (Ins[i].Flags.isSRet()) {
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OriginalArgWasF128.push_back(false);
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OriginalArgWasFloat.push_back(false);
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continue;
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}
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@ -15,6 +15,8 @@
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@struct_byte = global {i8} zeroinitializer
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@struct_2byte = global {i8,i8} zeroinitializer
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@struct_3xi16 = global {[3 x i16]} zeroinitializer
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@struct_6xi32 = global {[6 x i32]} zeroinitializer
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@struct_128xi16 = global {[128 x i16]} zeroinitializer
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declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i32, i1)
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@ -136,3 +138,95 @@ entry:
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; N64-BE-DAG: lhu [[R3:\$[0-9]+]], 4([[PTR]])
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; N64-BE-DAG: or [[R4:\$[0-9]+]], [[R3]], [[R2]]
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; N32-BE-DAG: dsll $2, [[R4]], 16
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; Ensure that large structures (>128-bit) are returned indirectly.
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; We pick an extremely large structure so we don't have to match inlined memcpy's.
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define void @ret_struct_128xi16({[128 x i16]}* sret %returnval) {
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entry:
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%0 = bitcast {[128 x i16]}* %returnval to i8*
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call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* bitcast ({[128 x i16]}* @struct_128xi16 to i8*), i64 256, i32 2, i1 false)
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ret void
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}
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; ALL-LABEL: ret_struct_128xi16:
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; sret pointer is already in $4
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; O32-DAG: lui [[PTR:\$[0-9]+]], %hi(struct_128xi16)
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; O32-DAG: addiu $5, [[PTR]], %lo(struct_128xi16)
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; O32: jal memcpy
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; sret pointer is already in $4
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; N32-DAG: lui [[PTR_HI:\$[0-9]+]], %hi(struct_128xi16)
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; N32-DAG: addiu [[PTR:\$[0-9]+]], [[PTR_HI]], %lo(struct_128xi16)
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; FIXME: This signext isn't necessary. Like integers, pointers are
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; but unlike integers, pointers cannot have the signext attribute.
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; N32-DAG: sll $5, [[PTR]], 0
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; N32: jal memcpy
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; sret pointer is already in $4
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; N64-DAG: ld $5, %got_disp(struct_128xi16)(
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; N64-DAG: ld $25, %call16(memcpy)(
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; N64: jalr $25
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; Ensure that large structures (>128-bit) are returned indirectly.
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; This will generate inlined memcpy's anyway so pick the smallest large
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; structure
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; This time we let the backend lower the sret argument.
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define {[6 x i32]} @ret_struct_6xi32() {
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entry:
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%0 = load volatile {[6 x i32]}* @struct_6xi32, align 2
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ret {[6 x i32]} %0
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}
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; ALL-LABEL: ret_struct_6xi32:
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; sret pointer is already in $4
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; O32-DAG: lui [[PTR_HI:\$[0-9]+]], %hi(struct_6xi32)
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; O32-DAG: addiu [[PTR:\$[0-9]+]], [[PTR_HI]], %lo(struct_6xi32)
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; O32-DAG: lw [[T0:\$[0-9]+]], %lo(struct_6xi32)([[PTR]])
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; O32-DAG: lw [[T1:\$[0-9]+]], 4([[PTR]])
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; O32-DAG: lw [[T2:\$[0-9]+]], 8([[PTR]])
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; O32-DAG: lw [[T3:\$[0-9]+]], 12([[PTR]])
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; O32-DAG: lw [[T4:\$[0-9]+]], 16([[PTR]])
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; O32-DAG: lw [[T5:\$[0-9]+]], 20([[PTR]])
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; O32-DAG: sw [[T0]], 0($4)
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; O32-DAG: sw [[T1]], 4($4)
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; O32-DAG: sw [[T2]], 8($4)
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; O32-DAG: sw [[T3]], 12($4)
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; O32-DAG: sw [[T4]], 16($4)
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; O32-DAG: sw [[T5]], 20($4)
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; FIXME: This signext isn't necessary. Like integers, pointers are
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; but unlike integers, pointers cannot have the signext attribute.
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; In this case we don't have anywhere to put the signext either since
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; the sret argument is invented by the backend.
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; N32-DAG: sll [[RET_PTR:\$[0-9]+]], $4, 0
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; N32-DAG: lui [[PTR_HI:\$[0-9]+]], %hi(struct_6xi32)
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; N32-DAG: addiu [[PTR:\$[0-9]+]], [[PTR_HI]], %lo(struct_6xi32)
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; N32-DAG: lw [[T0:\$[0-9]+]], %lo(struct_6xi32)([[PTR]])
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; N32-DAG: lw [[T1:\$[0-9]+]], 4([[PTR]])
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; N32-DAG: lw [[T2:\$[0-9]+]], 8([[PTR]])
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; N32-DAG: lw [[T3:\$[0-9]+]], 12([[PTR]])
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; N32-DAG: lw [[T4:\$[0-9]+]], 16([[PTR]])
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; N32-DAG: lw [[T5:\$[0-9]+]], 20([[PTR]])
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; N32-DAG: sw [[T0]], 0([[RET_PTR]])
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; N32-DAG: sw [[T1]], 4([[RET_PTR]])
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; N32-DAG: sw [[T2]], 8([[RET_PTR]])
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; N32-DAG: sw [[T3]], 12([[RET_PTR]])
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; N32-DAG: sw [[T4]], 16([[RET_PTR]])
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; N32-DAG: sw [[T5]], 20([[RET_PTR]])
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; sret pointer is already in $4
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; N64-DAG: ld [[PTR:\$[0-9]+]], %got_disp(struct_6xi32)(
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; N64-DAG: lw [[T0:\$[0-9]+]], 0([[PTR]])
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; N64-DAG: lw [[T1:\$[0-9]+]], 4([[PTR]])
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; N64-DAG: lw [[T2:\$[0-9]+]], 8([[PTR]])
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; N64-DAG: lw [[T3:\$[0-9]+]], 12([[PTR]])
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; N64-DAG: lw [[T4:\$[0-9]+]], 16([[PTR]])
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; N64-DAG: lw [[T5:\$[0-9]+]], 20([[PTR]])
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; N64-DAG: sw [[T0]], 0($4)
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; N64-DAG: sw [[T1]], 4($4)
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; N64-DAG: sw [[T2]], 8($4)
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; N64-DAG: sw [[T3]], 12($4)
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; N64-DAG: sw [[T4]], 16($4)
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; N64-DAG: sw [[T5]], 20($4)
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