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Propagate DebugLoc info for spiller call-backs.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64329 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling 2009-02-11 21:51:19 +00:00
parent c7fa16f782
commit fbef3101a5
1 changed files with 69 additions and 42 deletions
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111
lib/Target/X86/X86InstrInfo.cpp
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@ -905,6 +905,9 @@ void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned DestReg,
const MachineInstr *Orig) const {
DebugLoc DL = DebugLoc::getUnknownLoc();
if (I != MBB.end()) DL = I->getDebugLoc();
unsigned SubIdx = Orig->getOperand(0).isReg()
? Orig->getOperand(0).getSubReg() : 0;
bool ChangeSubIdx = SubIdx != 0;
@ -931,7 +934,7 @@ void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
case X86::MOV32r0: Opc = X86::MOV32ri; break;
case X86::MOV64r0: Opc = X86::MOV64ri32; break;
}
BuildMI(MBB, I, get(Opc), DestReg).addImm(0);
BuildMI(MBB, I, DL, get(Opc), DestReg).addImm(0);
Emitted = true;
}
break;
@ -1038,7 +1041,8 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
if (B != C) return 0;
unsigned A = MI->getOperand(0).getReg();
unsigned M = MI->getOperand(3).getImm();
NewMI = BuildMI(MF, get(X86::PSHUFDri)).addReg(A, true, false, false, isDead)
NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
.addReg(A, true, false, false, isDead)
.addReg(B, false, false, isKill).addImm(M);
break;
}
@ -1049,7 +1053,8 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
unsigned ShAmt = MI->getOperand(2).getImm();
if (ShAmt == 0 || ShAmt >= 4) return 0;
NewMI = BuildMI(MF, get(X86::LEA64r)).addReg(Dest, true, false, false, isDead)
NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
.addReg(Dest, true, false, false, isDead)
.addReg(0).addImm(1 << ShAmt).addReg(Src, false, false, isKill).addImm(0);
break;
}
@ -1062,7 +1067,8 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() ?
X86::LEA64_32r : X86::LEA32r;
NewMI = BuildMI(MF, get(Opc)).addReg(Dest, true, false, false, isDead)
NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
.addReg(Dest, true, false, false, isDead)
.addReg(0).addImm(1 << ShAmt)
.addReg(Src, false, false, isKill).addImm(0);
break;
@ -1084,17 +1090,21 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
// Build and insert into an implicit UNDEF value. This is OK because
// well be shifting and then extracting the lower 16-bits.
BuildMI(*MFI, MBBI, get(X86::IMPLICIT_DEF), leaInReg);
MachineInstr *InsMI = BuildMI(*MFI, MBBI, get(X86::INSERT_SUBREG),leaInReg)
BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
MachineInstr *InsMI =
BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::INSERT_SUBREG),leaInReg)
.addReg(leaInReg).addReg(Src, false, false, isKill)
.addImm(X86::SUBREG_16BIT);
NewMI = BuildMI(*MFI, MBBI, get(Opc), leaOutReg).addReg(0).addImm(1 << ShAmt)
NewMI = BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(Opc), leaOutReg)
.addReg(0).addImm(1 << ShAmt)
.addReg(leaInReg, false, false, true).addImm(0);
MachineInstr *ExtMI = BuildMI(*MFI, MBBI, get(X86::EXTRACT_SUBREG))
MachineInstr *ExtMI =
BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::EXTRACT_SUBREG))
.addReg(Dest, true, false, false, isDead)
.addReg(leaOutReg, false, false, true).addImm(X86::SUBREG_16BIT);
if (LV) {
// Update live variables
LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
@ -1106,7 +1116,8 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
}
return ExtMI;
} else {
NewMI = BuildMI(MF, get(X86::LEA16r)).addReg(Dest, true, false, false, isDead)
NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
.addReg(Dest, true, false, false, isDead)
.addReg(0).addImm(1 << ShAmt)
.addReg(Src, false, false, isKill).addImm(0);
}
@ -1128,7 +1139,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
: (is64Bit ? X86::LEA64_32r : X86::LEA32r);
NewMI = addRegOffset(BuildMI(MF, get(Opc))
NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
.addReg(Dest, true, false, false, isDead),
Src, isKill, 1);
break;
@ -1137,7 +1148,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
case X86::INC64_16r:
if (DisableLEA16) return 0;
assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
NewMI = addRegOffset(BuildMI(MF, get(X86::LEA16r))
NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
.addReg(Dest, true, false, false, isDead),
Src, isKill, 1);
break;
@ -1147,7 +1158,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
: (is64Bit ? X86::LEA64_32r : X86::LEA32r);
NewMI = addRegOffset(BuildMI(MF, get(Opc))
NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
.addReg(Dest, true, false, false, isDead),
Src, isKill, -1);
break;
@ -1156,7 +1167,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
case X86::DEC64_16r:
if (DisableLEA16) return 0;
assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
NewMI = addRegOffset(BuildMI(MF, get(X86::LEA16r))
NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
.addReg(Dest, true, false, false, isDead),
Src, isKill, -1);
break;
@ -1167,7 +1178,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
: (is64Bit ? X86::LEA64_32r : X86::LEA32r);
unsigned Src2 = MI->getOperand(2).getReg();
bool isKill2 = MI->getOperand(2).isKill();
NewMI = addRegReg(BuildMI(MF, get(Opc))
NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(Opc))
.addReg(Dest, true, false, false, isDead),
Src, isKill, Src2, isKill2);
if (LV && isKill2)
@ -1179,7 +1190,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
unsigned Src2 = MI->getOperand(2).getReg();
bool isKill2 = MI->getOperand(2).isKill();
NewMI = addRegReg(BuildMI(MF, get(X86::LEA16r))
NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
.addReg(Dest, true, false, false, isDead),
Src, isKill, Src2, isKill2);
if (LV && isKill2)
@ -1190,7 +1201,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
case X86::ADD64ri8:
assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
if (MI->getOperand(2).isImm())
NewMI = addRegOffset(BuildMI(MF, get(X86::LEA64r))
NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
.addReg(Dest, true, false, false, isDead),
Src, isKill, MI->getOperand(2).getImm());
break;
@ -1199,7 +1210,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
if (MI->getOperand(2).isImm()) {
unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
NewMI = addRegOffset(BuildMI(MF, get(Opc))
NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
.addReg(Dest, true, false, false, isDead),
Src, isKill, MI->getOperand(2).getImm());
}
@ -1209,7 +1220,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
if (DisableLEA16) return 0;
assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
if (MI->getOperand(2).isImm())
NewMI = addRegOffset(BuildMI(MF, get(X86::LEA16r))
NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
.addReg(Dest, true, false, false, isDead),
Src, isKill, MI->getOperand(2).getImm());
break;
@ -1227,7 +1238,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
unsigned Opc = MIOpc == X86::SHL64ri ? X86::LEA64r
: (MIOpc == X86::SHL32ri
? (is64Bit ? X86::LEA64_32r : X86::LEA32r) : X86::LEA16r);
NewMI = addFullAddress(BuildMI(MF, get(Opc))
NewMI = addFullAddress(BuildMI(MF, MI->getDebugLoc(), get(Opc))
.addReg(Dest, true, false, false, isDead), AM);
if (isKill)
NewMI->getOperand(3).setIsKill(true);
@ -1668,6 +1679,9 @@ bool X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,
const TargetRegisterClass *SrcRC) const {
DebugLoc DL = DebugLoc::getUnknownLoc();
if (MI != MBB.end()) DL = MI->getDebugLoc();
if (DestRC == SrcRC) {
unsigned Opc;
if (DestRC == &X86::GR64RegClass) {
@ -1699,7 +1713,7 @@ bool X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
} else {
return false;
}
BuildMI(MBB, MI, get(Opc), DestReg).addReg(SrcReg);
BuildMI(MBB, MI, DL, get(Opc), DestReg).addReg(SrcReg);
return true;
}
@ -1708,24 +1722,24 @@ bool X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
if (SrcReg != X86::EFLAGS)
return false;
if (DestRC == &X86::GR64RegClass) {
BuildMI(MBB, MI, get(X86::PUSHFQ));
BuildMI(MBB, MI, get(X86::POP64r), DestReg);
BuildMI(MBB, MI, DL, get(X86::PUSHFQ));
BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
return true;
} else if (DestRC == &X86::GR32RegClass) {
BuildMI(MBB, MI, get(X86::PUSHFD));
BuildMI(MBB, MI, get(X86::POP32r), DestReg);
BuildMI(MBB, MI, DL, get(X86::PUSHFD));
BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
return true;
}
} else if (DestRC == &X86::CCRRegClass) {
if (DestReg != X86::EFLAGS)
return false;
if (SrcRC == &X86::GR64RegClass) {
BuildMI(MBB, MI, get(X86::PUSH64r)).addReg(SrcReg);
BuildMI(MBB, MI, get(X86::POPFQ));
BuildMI(MBB, MI, DL, get(X86::PUSH64r)).addReg(SrcReg);
BuildMI(MBB, MI, DL, get(X86::POPFQ));
return true;
} else if (SrcRC == &X86::GR32RegClass) {
BuildMI(MBB, MI, get(X86::PUSH32r)).addReg(SrcReg);
BuildMI(MBB, MI, get(X86::POPFD));
BuildMI(MBB, MI, DL, get(X86::PUSH32r)).addReg(SrcReg);
BuildMI(MBB, MI, DL, get(X86::POPFD));
return true;
}
}
@ -1747,7 +1761,7 @@ bool X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
return false;
Opc = isST0 ? X86::FpGET_ST0_80 : X86::FpGET_ST1_80;
}
BuildMI(MBB, MI, get(Opc), DestReg);
BuildMI(MBB, MI, DL, get(Opc), DestReg);
return true;
}
@ -1768,7 +1782,7 @@ bool X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
return false;
Opc = isST0 ? X86::FpSET_ST0_80 : X86::FpSET_ST1_80;
}
BuildMI(MBB, MI, get(Opc)).addReg(SrcReg);
BuildMI(MBB, MI, DL, get(Opc)).addReg(SrcReg);
return true;
}
@ -1822,8 +1836,10 @@ void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
bool isAligned = (RI.getStackAlignment() >= 16) ||
RI.needsStackRealignment(MF);
unsigned Opc = getStoreRegOpcode(RC, isAligned);
addFrameReference(BuildMI(MBB, MI, get(Opc)), FrameIdx)
.addReg(SrcReg, false, false, isKill);
DebugLoc DL = DebugLoc::getUnknownLoc();
if (MI != MBB.end()) DL = MI->getDebugLoc();
addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
.addReg(SrcReg, false, false, isKill);
}
void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
@ -1887,7 +1903,9 @@ void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
bool isAligned = (RI.getStackAlignment() >= 16) ||
RI.needsStackRealignment(MF);
unsigned Opc = getLoadRegOpcode(RC, isAligned);
addFrameReference(BuildMI(MBB, MI, get(Opc), DestReg), FrameIdx);
DebugLoc DL = DebugLoc::getUnknownLoc();
if (MI != MBB.end()) DL = MI->getDebugLoc();
addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
}
void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
@ -1904,11 +1922,14 @@ void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
}
bool X86InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
MachineBasicBlock::iterator MI,
const std::vector<CalleeSavedInfo> &CSI) const {
if (CSI.empty())
return false;
DebugLoc DL = DebugLoc::getUnknownLoc();
if (MI != MBB.end()) DL = MI->getDebugLoc();
bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
unsigned SlotSize = is64Bit ? 8 : 4;
@ -1928,17 +1949,20 @@ bool X86InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
}
bool X86InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
MachineBasicBlock::iterator MI,
const std::vector<CalleeSavedInfo> &CSI) const {
if (CSI.empty())
return false;
DebugLoc DL = DebugLoc::getUnknownLoc();
if (MI != MBB.end()) DL = MI->getDebugLoc();
bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
unsigned Opc = is64Bit ? X86::POP64r : X86::POP32r;
for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
unsigned Reg = CSI[i].getReg();
BuildMI(MBB, MI, get(Opc), Reg);
BuildMI(MBB, MI, DL, get(Opc), Reg);
}
return true;
}
@ -1998,7 +2022,7 @@ static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
const SmallVectorImpl<MachineOperand> &MOs,
MachineInstr *MI) {
MachineFunction &MF = *MI->getParent()->getParent();
MachineInstrBuilder MIB = BuildMI(MF, TII.get(Opcode));
MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
unsigned NumAddrOps = MOs.size();
for (unsigned i = 0; i != NumAddrOps; ++i)
@ -2258,7 +2282,7 @@ bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
SmallVectorImpl<MachineInstr*> &NewMIs) const {
SmallVectorImpl<MachineInstr*> &NewMIs) const {
DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
MemOp2RegOpTable.find((unsigned*)MI->getOpcode());
if (I == MemOp2RegOpTable.end())
@ -2361,7 +2385,7 @@ bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
bool
X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
SmallVectorImpl<SDNode*> &NewNodes) const {
SmallVectorImpl<SDNode*> &NewNodes) const {
if (!N->isMachineOpcode())
return false;
@ -3078,13 +3102,16 @@ unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
// Insert the set of GlobalBaseReg into the first MBB of the function
MachineBasicBlock &FirstMBB = MF->front();
MachineBasicBlock::iterator MBBI = FirstMBB.begin();
DebugLoc DL = DebugLoc::getUnknownLoc();
if (MBBI != FirstMBB.end()) DL = MBBI->getDebugLoc();
MachineRegisterInfo &RegInfo = MF->getRegInfo();
unsigned PC = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
const TargetInstrInfo *TII = TM.getInstrInfo();
// Operand of MovePCtoStack is completely ignored by asm printer. It's
// only used in JIT code emission as displacement to pc.
BuildMI(FirstMBB, MBBI, TII->get(X86::MOVPC32r), PC).addImm(0);
BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC)
.addImm(0);
// If we're using vanilla 'GOT' PIC style, we should use relative addressing
// not to pc, but to _GLOBAL_ADDRESS_TABLE_ external
@ -3092,7 +3119,7 @@ unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
TM.getSubtarget<X86Subtarget>().isPICStyleGOT()) {
GlobalBaseReg =
RegInfo.createVirtualRegister(X86::GR32RegisterClass);
BuildMI(FirstMBB, MBBI, TII->get(X86::ADD32ri), GlobalBaseReg)
BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
.addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_");
} else {
GlobalBaseReg = PC;