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ARM: stop passing unused values up the TableGen hierarchy.
It's bad enough that I have to look up 5 different levels of TableGen class definitions to work out what bits go where in a simple NEON instruction anyway, without having to keep track of umpteen unused parameters. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207420 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2029,7 +2029,7 @@ class N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
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// Same as N2V but not predicated.
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class N2Vnp<bits<2> op19_18, bits<2> op17_16, bits<3> op10_8, bit op7, bit op6,
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dag oops, dag iops, InstrItinClass itin, string OpcodeStr,
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string Dt, ValueType ResTy, ValueType OpTy, list<dag> pattern>
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string Dt, list<dag> pattern>
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: NeonInp<oops, iops, AddrModeNone, IndexModeNone, N2RegFrm, itin,
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OpcodeStr, Dt, "$Vd, $Vm", "", pattern> {
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bits<5> Vd;
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@ -2138,8 +2138,7 @@ class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
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class N3Vnp<bits<5> op27_23, bits<2> op21_20, bits<4> op11_8, bit op6,
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bit op4, dag oops, dag iops,Format f, InstrItinClass itin,
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string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
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SDPatternOperator IntOp, bit Commutable, list<dag> pattern>
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string OpcodeStr, string Dt, list<dag> pattern>
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: NeonInp<oops, iops, AddrModeNone, IndexModeNone, f, itin, OpcodeStr,
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Dt, "$Vd, $Vn, $Vm", "", pattern> {
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bits<5> Vd;
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@ -2456,14 +2456,14 @@ class N2VDIntnp<bits<2> op17_16, bits<3> op10_8, bit op7,
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InstrItinClass itin, string OpcodeStr, string Dt,
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ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
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: N2Vnp<0b10, op17_16, op10_8, op7, 0, (outs DPR:$Vd), (ins DPR:$Vm),
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itin, OpcodeStr, Dt, ResTy, OpTy,
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itin, OpcodeStr, Dt,
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[(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
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class N2VQIntnp<bits<2> op17_16, bits<3> op10_8, bit op7,
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InstrItinClass itin, string OpcodeStr, string Dt,
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ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
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: N2Vnp<0b10, op17_16, op10_8, op7, 1, (outs QPR:$Vd), (ins QPR:$Vm),
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itin, OpcodeStr, Dt, ResTy, OpTy,
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itin, OpcodeStr, Dt,
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[(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
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// Similar to NV2VQIntnp with some more encoding bits exposed (crypto).
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@ -2471,7 +2471,7 @@ class N2VQIntXnp<bits<2> op19_18, bits<2> op17_16, bits<3> op10_8, bit op6,
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bit op7, InstrItinClass itin, string OpcodeStr, string Dt,
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ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
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: N2Vnp<op19_18, op17_16, op10_8, op7, op6, (outs QPR:$Vd), (ins QPR:$Vm),
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itin, OpcodeStr, Dt, ResTy, OpTy,
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itin, OpcodeStr, Dt,
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[(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
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// Same as N2VQIntXnp but with Vd as a src register.
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@ -2480,7 +2480,7 @@ class N2VQIntX2np<bits<2> op19_18, bits<2> op17_16, bits<3> op10_8, bit op6,
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ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
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: N2Vnp<op19_18, op17_16, op10_8, op7, op6,
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(outs QPR:$Vd), (ins QPR:$src, QPR:$Vm),
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itin, OpcodeStr, Dt, ResTy, OpTy,
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itin, OpcodeStr, Dt,
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[(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src), (OpTy QPR:$Vm))))]> {
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let Constraints = "$src = $Vd";
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}
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@ -2654,7 +2654,6 @@ class N3VDIntnp<bits<5> op27_23, bits<2> op21_20, bits<4> op11_8, bit op6,
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SDPatternOperator IntOp, bit Commutable>
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: N3Vnp<op27_23, op21_20, op11_8, op6, op4,
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(outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin, OpcodeStr, Dt,
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ResTy, OpTy, IntOp, Commutable,
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[(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>;
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class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
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@ -2708,7 +2707,6 @@ class N3VQIntnp<bits<5> op27_23, bits<2> op21_20, bits<4> op11_8, bit op6,
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SDPatternOperator IntOp, bit Commutable>
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: N3Vnp<op27_23, op21_20, op11_8, op6, op4,
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(outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin, OpcodeStr, Dt,
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ResTy, OpTy, IntOp, Commutable,
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[(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>;
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// Same as N3VQIntnp but with Vd as a src register.
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@ -2717,8 +2715,8 @@ class N3VQInt3np<bits<5> op27_23, bits<2> op21_20, bits<4> op11_8, bit op6,
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string Dt, ValueType ResTy, ValueType OpTy,
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SDPatternOperator IntOp, bit Commutable>
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: N3Vnp<op27_23, op21_20, op11_8, op6, op4,
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(outs QPR:$Vd), (ins QPR:$src, QPR:$Vn, QPR:$Vm), f, itin, OpcodeStr,
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Dt, ResTy, OpTy, IntOp, Commutable,
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(outs QPR:$Vd), (ins QPR:$src, QPR:$Vn, QPR:$Vm),
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f, itin, OpcodeStr, Dt,
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[(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src), (OpTy QPR:$Vn),
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(OpTy QPR:$Vm))))]> {
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let Constraints = "$src = $Vd";
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@ -3038,7 +3036,6 @@ class N3VLIntnp<bits<5> op27_23, bits<2> op21_20, bits<4> op11_8, bit op6,
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SDPatternOperator IntOp, bit Commutable>
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: N3Vnp<op27_23, op21_20, op11_8, op6, op4,
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(outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin, OpcodeStr, Dt,
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ResTy, OpTy, IntOp, Commutable,
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[(set QPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>;
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class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
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