6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-07-25 13:24:46 +00:00
Code Issues Projects Releases Wiki Activity

[mips] Prevent %lo relocation being used on MSA loads and stores.

Browse Source 
Summary:
Parts of the compiler still believed MSA load/stores have a 16-bit offset when
it is actually 10-bit. Corrected this, and fixed a closely related issue this
uncovered where load/stores with 10-bit and 12-bit offsets (MSA and microMIPS
respectively) could not load/store using offsets from the stack/frame pointer.
They accepted frameindex+offset, but not frameindex by itself.

Reviewers: jacksprat, matheusalmeida

Reviewed By: jacksprat

Differential Revision: http://llvm-reviews.chandlerc.com/D2888

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202717 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders
2014-03-03 14:31:21 +00:00
parent c1e634da0c
commit fc210ac1ef
11 changed files with 164 additions and 106 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
test/CodeGen/Mips/msa/arithmetic_float.ll
View File

@@ -295,7 +295,8 @@ define void @fexp2_v2f64_2(<2 x double>* %c, <2 x double>* %a) nounwind {
; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
%2 = tail call <2 x double> @llvm.exp2.v2f64 (<2 x double> %1)
%3 = fmul <2 x double> <double 2.0, double 2.0>, %2
; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], %lo(
; CHECK-DAG: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0([[G_PTR]])
; CHECK-DAG: fexp2.d [[R4:\$w[0-9]+]], [[R3]], [[R1]]
store <2 x double> %3, <2 x double>* %c
; CHECK-DAG: st.d [[R4]], 0($4)

30
test/CodeGen/Mips/msa/basic_operations.ll
View File

@@ -18,10 +18,12 @@ define void @const_v16i8() nounwind {
; MIPS32-AE: ldi.b [[R1:\$w[0-9]+]], 1
store volatile <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 31>, <16 x i8>*@v16i8
; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], %lo(
; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 0([[G_PTR]])
store volatile <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6>, <16 x i8>*@v16i8
; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], %lo(
; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 0([[G_PTR]])
store volatile <16 x i8> <i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0>, <16 x i8>*@v16i8
; MIPS32-BE: ldi.h [[R1:\$w[0-9]+]], 256
@@ -35,7 +37,8 @@ define void @const_v16i8() nounwind {
; MIPS32-AE-DAG: fill.w [[R1:\$w[0-9]+]], [[R2]]
store volatile <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, <16 x i8>*@v16i8
; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], %lo(
; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 0([[G_PTR]])
ret void
; MIPS32-AE: .size const_v16i8
@@ -51,7 +54,8 @@ define void @const_v8i16() nounwind {
; MIPS32-AE: ldi.h [[R1:\$w[0-9]+]], 1
store volatile <8 x i16> <i16 1, i16 1, i16 1, i16 2, i16 1, i16 1, i16 1, i16 31>, <8 x i16>*@v8i16
; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], %lo(
; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 0([[G_PTR]])
store volatile <8 x i16> <i16 1028, i16 1028, i16 1028, i16 1028, i16 1028, i16 1028, i16 1028, i16 1028>, <8 x i16>*@v8i16
; MIPS32-AE: ldi.b [[R1:\$w[0-9]+]], 4
@@ -64,7 +68,8 @@ define void @const_v8i16() nounwind {
; MIPS32-AE-DAG: fill.w [[R1:\$w[0-9]+]], [[R2]]
store volatile <8 x i16> <i16 1, i16 2, i16 3, i16 4, i16 1, i16 2, i16 3, i16 4>, <8 x i16>*@v8i16
; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], %lo(
; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 0([[G_PTR]])
ret void
; MIPS32-AE: .size const_v8i16
@@ -80,7 +85,8 @@ define void @const_v4i32() nounwind {
; MIPS32-AE: ldi.w [[R1:\$w[0-9]+]], 1
store volatile <4 x i32> <i32 1, i32 1, i32 1, i32 31>, <4 x i32>*@v4i32
; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], %lo(
; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]])
store volatile <4 x i32> <i32 16843009, i32 16843009, i32 16843009, i32 16843009>, <4 x i32>*@v4i32
; MIPS32-AE: ldi.b [[R1:\$w[0-9]+]], 1
@@ -89,10 +95,12 @@ define void @const_v4i32() nounwind {
; MIPS32-AE: ldi.h [[R1:\$w[0-9]+]], 1
store volatile <4 x i32> <i32 1, i32 2, i32 1, i32 2>, <4 x i32>*@v4i32
; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], %lo(
; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]])
store volatile <4 x i32> <i32 3, i32 4, i32 5, i32 6>, <4 x i32>*@v4i32
; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], %lo(
; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]])
ret void
; MIPS32-AE: .size const_v4i32
@@ -117,10 +125,12 @@ define void @const_v2i64() nounwind {
; MIPS32-AE: ldi.d [[R1:\$w[0-9]+]], 1
store volatile <2 x i64> <i64 1, i64 31>, <2 x i64>*@v2i64
; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], %lo(
; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]])
store volatile <2 x i64> <i64 3, i64 4>, <2 x i64>*@v2i64
; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], %lo(
; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]])
ret void
; MIPS32-AE: .size const_v2i64

27
test/CodeGen/Mips/msa/basic_operations_float.ll
View File

@@ -17,7 +17,8 @@ define void @const_v4f32() nounwind {
; MIPS32: fill.w [[R2:\$w[0-9]+]], [[R1]]
store volatile <4 x float> <float 1.0, float 1.0, float 1.0, float 31.0>, <4 x float>*@v4f32
; MIPS32: ld.w [[R1:\$w[0-9]+]], %lo(
; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
; MIPS32: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]])
store volatile <4 x float> <float 65537.0, float 65537.0, float 65537.0, float 65537.0>, <4 x float>*@v4f32
; MIPS32: lui [[R1:\$[0-9]+]], 18304
@@ -25,10 +26,12 @@ define void @const_v4f32() nounwind {
; MIPS32: fill.w [[R3:\$w[0-9]+]], [[R2]]
store volatile <4 x float> <float 1.0, float 2.0, float 1.0, float 2.0>, <4 x float>*@v4f32
; MIPS32: ld.w [[R1:\$w[0-9]+]], %lo(
; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
; MIPS32: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]])
store volatile <4 x float> <float 3.0, float 4.0, float 5.0, float 6.0>, <4 x float>*@v4f32
; MIPS32: ld.w [[R1:\$w[0-9]+]], %lo(
; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
; MIPS32: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]])
ret void
; MIPS32: .size const_v4f32
@@ -41,22 +44,28 @@ define void @const_v2f64() nounwind {
; MIPS32: ldi.b [[R1:\$w[0-9]+]], 0
store volatile <2 x double> <double 72340172838076673.0, double 72340172838076673.0>, <2 x double>*@v2f64
; MIPS32: ld.d [[R1:\$w[0-9]+]], %lo(
; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
; MIPS32: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]])
store volatile <2 x double> <double 281479271743489.0, double 281479271743489.0>, <2 x double>*@v2f64
; MIPS32: ld.d [[R1:\$w[0-9]+]], %lo(
; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
; MIPS32: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]])
store volatile <2 x double> <double 4294967297.0, double 4294967297.0>, <2 x double>*@v2f64
; MIPS32: ld.d [[R1:\$w[0-9]+]], %lo(
; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
; MIPS32: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]])
store volatile <2 x double> <double 1.0, double 1.0>, <2 x double>*@v2f64
; MIPS32: ld.d [[R1:\$w[0-9]+]], %lo(
; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
; MIPS32: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]])
store volatile <2 x double> <double 1.0, double 31.0>, <2 x double>*@v2f64
; MIPS32: ld.d [[R1:\$w[0-9]+]], %lo(
; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
; MIPS32: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]])
store volatile <2 x double> <double 3.0, double 4.0>, <2 x double>*@v2f64
; MIPS32: ld.d [[R1:\$w[0-9]+]], %lo(
; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
; MIPS32: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]])
ret void
; MIPS32: .size const_v2f64

3
test/CodeGen/Mips/msa/shift-dagcombine.ll
View File

@@ -37,7 +37,8 @@ define void @lshr_v4i32(<4 x i32>* %c) nounwind {
%2 = lshr <4 x i32> <i32 -2, i32 -4, i32 -8, i32 -16>,
<i32 0, i32 1, i32 2, i32 3>
; CHECK-NOT: srl
; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], %lo
; CHECK-DAG: addiu [[CPOOL:\$[0-9]+]], {{.*}}, %lo($
; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0([[CPOOL]])
; CHECK-NOT: srl
store volatile <4 x i32> %2, <4 x i32>* %c
; CHECK-DAG: st.w [[R1]], 0($4)

30
test/CodeGen/Mips/msa/shuffle.ll
View File

@@ -7,7 +7,8 @@ define void @vshf_v16i8_0(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind
%1 = load <16 x i8>* %a
; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
%2 = shufflevector <16 x i8> %1, <16 x i8> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], %lo
; CHECK-DAG: addiu [[PTR_A:\$[0-9]+]], {{.*}}, %lo($
; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], 0([[PTR_A]])
; CHECK-DAG: vshf.b [[R3]], [[R1]], [[R1]]
store <16 x i8> %2, <16 x i8>* %c
; CHECK-DAG: st.b [[R3]], 0($4)
@@ -37,7 +38,8 @@ define void @vshf_v16i8_2(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind
%2 = load <16 x i8>* %b
; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
%3 = shufflevector <16 x i8> %1, <16 x i8> %2, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 16>
; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], %lo
; CHECK-DAG: addiu [[PTR_A:\$[0-9]+]], {{.*}}, %lo($
; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], 0([[PTR_A]])
; CHECK-DAG: vshf.b [[R3]], [[R2]], [[R2]]
store <16 x i8> %3, <16 x i8>* %c
; CHECK-DAG: st.b [[R3]], 0($4)
@@ -54,7 +56,8 @@ define void @vshf_v16i8_3(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind
%2 = load <16 x i8>* %b
; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
%3 = shufflevector <16 x i8> %1, <16 x i8> %2, <16 x i32> <i32 17, i32 24, i32 25, i32 18, i32 19, i32 20, i32 28, i32 19, i32 1, i32 8, i32 9, i32 2, i32 3, i32 4, i32 12, i32 3>
; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], %lo
; CHECK-DAG: addiu [[PTR_A:\$[0-9]+]], {{.*}}, %lo($
; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], 0([[PTR_A]])
; CHECK-DAG: vshf.b [[R3]], [[R1]], [[R2]]
store <16 x i8> %3, <16 x i8>* %c
; CHECK-DAG: st.b [[R3]], 0($4)
@@ -83,7 +86,8 @@ define void @vshf_v8i16_0(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind
%1 = load <8 x i16>* %a
; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
%2 = shufflevector <8 x i16> %1, <8 x i16> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; CHECK-DAG: ld.h [[R3:\$w[0-9]+]], %lo
; CHECK-DAG: addiu [[PTR_A:\$[0-9]+]], {{.*}}, %lo($
; CHECK-DAG: ld.h [[R3:\$w[0-9]+]], 0([[PTR_A]])
; CHECK-DAG: vshf.h [[R3]], [[R1]], [[R1]]
store <8 x i16> %2, <8 x i16>* %c
; CHECK-DAG: st.h [[R3]], 0($4)
@@ -113,7 +117,8 @@ define void @vshf_v8i16_2(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind
%2 = load <8 x i16>* %b
; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
%3 = shufflevector <8 x i16> %1, <8 x i16> %2, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 8>
; CHECK-DAG: ld.h [[R3:\$w[0-9]+]], %lo
; CHECK-DAG: addiu [[PTR_A:\$[0-9]+]], {{.*}}, %lo($
; CHECK-DAG: ld.h [[R3:\$w[0-9]+]], 0([[PTR_A]])
; CHECK-DAG: vshf.h [[R3]], [[R2]], [[R2]]
store <8 x i16> %3, <8 x i16>* %c
; CHECK-DAG: st.h [[R3]], 0($4)
@@ -130,7 +135,8 @@ define void @vshf_v8i16_3(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind
%2 = load <8 x i16>* %b
; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
%3 = shufflevector <8 x i16> %1, <8 x i16> %2, <8 x i32> <i32 1, i32 8, i32 9, i32 2, i32 3, i32 4, i32 12, i32 3>
; CHECK-DAG: ld.h [[R3:\$w[0-9]+]], %lo
; CHECK-DAG: addiu [[PTR_A:\$[0-9]+]], {{.*}}, %lo($
; CHECK-DAG: ld.h [[R3:\$w[0-9]+]], 0([[PTR_A]])
; CHECK-DAG: vshf.h [[R3]], [[R1]], [[R2]]
store <8 x i16> %3, <8 x i16>* %c
; CHECK-DAG: st.h [[R3]], 0($4)
@@ -207,7 +213,8 @@ define void @vshf_v4i32_3(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind
%2 = load <4 x i32>* %b
; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
%3 = shufflevector <4 x i32> %1, <4 x i32> %2, <4 x i32> <i32 1, i32 5, i32 6, i32 4>
; CHECK-DAG: ld.w [[R3:\$w[0-9]+]], %lo
; CHECK-DAG: addiu [[PTR_A:\$[0-9]+]], {{.*}}, %lo($
; CHECK-DAG: ld.w [[R3:\$w[0-9]+]], 0([[PTR_A]])
; CHECK-DAG: vshf.w [[R3]], [[R1]], [[R2]]
store <4 x i32> %3, <4 x i32>* %c
; CHECK-DAG: st.w [[R3]], 0($4)
@@ -236,7 +243,8 @@ define void @vshf_v2i64_0(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind
%1 = load <2 x i64>* %a
; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
%2 = shufflevector <2 x i64> %1, <2 x i64> undef, <2 x i32> <i32 1, i32 0>
; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], %lo
; CHECK-DAG: addiu [[PTR_A:\$[0-9]+]], {{.*}}, %lo($
; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0([[PTR_A]])
; CHECK-DAG: vshf.d [[R3]], [[R1]], [[R1]]
store <2 x i64> %2, <2 x i64>* %c
; CHECK-DAG: st.d [[R3]], 0($4)
@@ -266,7 +274,8 @@ define void @vshf_v2i64_2(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind
%2 = load <2 x i64>* %b
; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
%3 = shufflevector <2 x i64> %1, <2 x i64> %2, <2 x i32> <i32 3, i32 2>
; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], %lo
; CHECK-DAG: addiu [[PTR_A:\$[0-9]+]], {{.*}}, %lo($
; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0([[PTR_A]])
; CHECK-DAG: vshf.d [[R3]], [[R2]], [[R2]]
store <2 x i64> %3, <2 x i64>* %c
; CHECK-DAG: st.d [[R3]], 0($4)
@@ -283,7 +292,8 @@ define void @vshf_v2i64_3(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind
%2 = load <2 x i64>* %b
; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
%3 = shufflevector <2 x i64> %1, <2 x i64> %2, <2 x i32> <i32 1, i32 2>
; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], %lo
; CHECK-DAG: addiu [[PTR_A:\$[0-9]+]], {{.*}}, %lo($
; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0([[PTR_A]])
; CHECK-DAG: vshf.d [[R3]], [[R1]], [[R2]]
store <2 x i64> %3, <2 x i64>* %c
; CHECK-DAG: st.d [[R3]], 0($4)