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[mips] Free up two values in SubtargetFeatureFlag by folding the redundant IsGP32/IsGP64 into IsGP32bit/IsGP64bit

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Summary:
We are currently very close to the 32-bit limit of the current assembler
implementation. This is because there is no way to represent an instruction
that is available in, for example, Mips3 or Mips32. We have to define a
feature bit that represents this.

This patch cleans up a pair of redundant feature bits and slightly postpones the
point we will reach the limit.

Reviewers: zoran.jovanovic, jkolek, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3703

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208685 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders 2014-05-13 11:17:46 +00:00
parent 56db241e8b
commit fc2427bcf8
2 changed files with 5 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
lib/Target/Mips/Mips64InstrInfo.td
View File

@ -429,7 +429,7 @@ def : MipsPat<(bswap GPR64:$rt), (DSHD (DSBH GPR64:$rt))>;
//===----------------------------------------------------------------------===//
def : MipsInstAlias<"move $dst, $src",
(DADDu GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64), 1>,
Requires<[IsGP64]>;
GPR_64;
def : MipsInstAlias<"daddu $rs, $rt, $imm",
(DADDiu GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm),
0>;

9
lib/Target/Mips/MipsInstrInfo.td
View File

@ -170,10 +170,6 @@ def IsGP32bit : Predicate<"!Subtarget.isGP64bit()">,
AssemblerPredicate<"!FeatureGP64Bit">;
def HasMips64 : Predicate<"Subtarget.hasMips64()">,
AssemblerPredicate<"FeatureMips64">;
def IsGP32 : Predicate<"!Subtarget.isGP64()">,
AssemblerPredicate<"!FeatureGP64Bit">;
def IsGP64 : Predicate<"Subtarget.isGP64()">,
AssemblerPredicate<"FeatureGP64Bit">;
def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
AssemblerPredicate<"FeatureMips64r2">;
def HasMips64r6 : Predicate<"Subtarget.hasMips64r6()">,
@ -205,6 +201,7 @@ def IsNotNaCl : Predicate<"!Subtarget.isTargetNaCl()">;
// They are mutually exclusive.
//===----------------------------------------------------------------------===//
class GPR_32 { list<Predicate> GPRPredicates = [IsGP32bit]; }
class GPR_64 { list<Predicate> GPRPredicates = [IsGP64bit]; }
//===----------------------------------------------------------------------===//
@ -1242,7 +1239,9 @@ def TLBWR : TLB<"tlbwr">, COP0_TLB_FM<0x06>;
//===----------------------------------------------------------------------===//
def : MipsInstAlias<"move $dst, $src",
(ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>,
Requires<[IsGP32, NotInMicroMips]>;
GPR_32 {
let AdditionalPredicates = [NotInMicroMips];
}
def : MipsInstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>;
def : MipsInstAlias<"addu $rs, $rt, $imm",
(ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;