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R600/SI: Fix extra whitespace in asm str

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This slipped in in r214467, so something like

V_MOV_B32_e32  v0, ... is now printed with 2 spaces
between the instruction name and first operand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214660 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault 2014-08-03 05:27:14 +00:00
parent 3d5463d81f
commit fc65cf649c
2 changed files with 16 additions and 1 deletions
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2
lib/Target/R600/SIInstrInfo.td
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@ -442,7 +442,7 @@ class VOPProfile <list<ValueType> _ArgVT> {
field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
HasModifiers>.ret;
field string Asm32 = "_e32 "#getAsm32<NumSrcArgs>.ret;
field string Asm32 = "_e32"#getAsm32<NumSrcArgs>.ret;
field string Asm64 = getAsm64<NumSrcArgs, HasModifiers>.ret;
}

15
test/CodeGen/R600/operand-spacing.ll Normal file
View File

@ -0,0 +1,15 @@
; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=SI %s
; Make sure there isn't an extra space between the instruction name and first operands.
; SI-LABEL: @add_f32
; SI-DAG: S_LOAD_DWORD [[SREGA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
; SI-DAG: S_LOAD_DWORD [[SREGB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
; SI: V_MOV_B32_e32 [[VREGB:v[0-9]+]], [[SREGB]]
; SI: V_ADD_F32_e32 [[RESULT:v[0-9]+]], [[SREGA]], [[VREGB]]
; SI: BUFFER_STORE_DWORD [[RESULT]],
define void @add_f32(float addrspace(1)* %out, float %a, float %b) {
%result = fadd float %a, %b
store float %result, float addrspace(1)* %out
ret void
}