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https://github.com/c64scene-ar/llvm-6502.git
synced 2025-03-06 05:33:28 +00:00
switch LowerFastCCArguments over to using the autogenerated Fastcall description.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34733 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
011bcc8cdd
commit
fc664c1bc0
@ -601,66 +601,6 @@ static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
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return VReg;
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}
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/// HowToPassArgument - Returns how an formal argument of the specified type
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/// should be passed. If it is through stack, returns the size of the stack
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/// slot; if it is through integer or XMM register, returns the number of
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/// integer or XMM registers are needed.
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static void
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HowToPassCallArgument(MVT::ValueType ObjectVT,
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bool ArgInReg,
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unsigned NumIntRegs, unsigned NumXMMRegs,
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unsigned MaxNumIntRegs,
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unsigned &ObjSize, unsigned &ObjIntRegs,
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unsigned &ObjXMMRegs) {
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ObjSize = 0;
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ObjIntRegs = 0;
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ObjXMMRegs = 0;
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if (MaxNumIntRegs>3) {
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// We don't have too much registers on ia32! :)
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MaxNumIntRegs = 3;
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}
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switch (ObjectVT) {
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default: assert(0 && "Unhandled argument type!");
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case MVT::i8:
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if (ArgInReg && (NumIntRegs < MaxNumIntRegs))
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ObjIntRegs = 1;
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else
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ObjSize = 1;
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break;
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case MVT::i16:
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if (ArgInReg && (NumIntRegs < MaxNumIntRegs))
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ObjIntRegs = 1;
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else
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ObjSize = 2;
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break;
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case MVT::i32:
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if (ArgInReg && (NumIntRegs < MaxNumIntRegs))
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ObjIntRegs = 1;
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else
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ObjSize = 4;
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break;
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case MVT::f32:
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ObjSize = 4;
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break;
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case MVT::f64:
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ObjSize = 8;
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break;
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case MVT::v16i8:
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case MVT::v8i16:
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case MVT::v4i32:
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case MVT::v2i64:
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case MVT::v4f32:
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case MVT::v2f64:
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if (NumXMMRegs < 4)
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ObjXMMRegs = 1;
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else
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ObjSize = 16;
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break;
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}
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}
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SDOperand X86TargetLowering::LowerCCCArguments(SDOperand Op, SelectionDAG &DAG,
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bool isStdCall) {
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unsigned NumArgs = Op.Val->getNumValues() - 1;
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@ -929,138 +869,83 @@ X86TargetLowering::LowerFastCCArguments(SDOperand Op, SelectionDAG &DAG) {
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MachineFunction &MF = DAG.getMachineFunction();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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SDOperand Root = Op.getOperand(0);
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SmallVector<SDOperand, 8> ArgValues;
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// Add DAG nodes to load the arguments... On entry to a function the stack
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// frame looks like this:
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//
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// [ESP] -- return address
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// [ESP + 4] -- first nonreg argument (leftmost lexically)
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// [ESP + 8] -- second nonreg argument, if 1st argument is <= 4 bytes in size
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// ...
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unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
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// Keep track of the number of integer regs passed so far. This can be either
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// 0 (neither EAX/ECX or EDX used), 1 (EAX/ECX is used) or 2 (EAX/ECX and EDX
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// are both used).
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unsigned NumIntRegs = 0;
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unsigned NumXMMRegs = 0; // XMM regs used for parameter passing.
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static const unsigned XMMArgRegs[] = {
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X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
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};
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static const unsigned GPRArgRegs[][2] = {
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{ X86::CL, X86::DL },
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{ X86::CX, X86::DX },
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{ X86::ECX, X86::EDX }
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};
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static const TargetRegisterClass* GPRClasses[3] = {
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X86::GR8RegisterClass, X86::GR16RegisterClass, X86::GR32RegisterClass
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};
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for (unsigned i = 0; i < NumArgs; ++i) {
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MVT::ValueType ObjectVT = Op.getValue(i).getValueType();
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unsigned ArgIncrement = 4;
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unsigned ObjSize = 0;
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unsigned ObjXMMRegs = 0;
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unsigned ObjIntRegs = 0;
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unsigned Reg = 0;
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SDOperand ArgValue;
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HowToPassCallArgument(ObjectVT,
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true, // Use as much registers as possible
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NumIntRegs, NumXMMRegs, 2,
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ObjSize, ObjIntRegs, ObjXMMRegs);
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if (ObjSize > 4)
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ArgIncrement = ObjSize;
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if (ObjIntRegs || ObjXMMRegs) {
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switch (ObjectVT) {
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default: assert(0 && "Unhandled argument type!");
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case MVT::i8:
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case MVT::i16:
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case MVT::i32: {
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unsigned RegToUse = GPRArgRegs[ObjectVT-MVT::i8][NumIntRegs];
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Reg = AddLiveIn(MF, RegToUse, GPRClasses[ObjectVT-MVT::i8]);
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ArgValue = DAG.getCopyFromReg(Root, Reg, ObjectVT);
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break;
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}
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case MVT::v16i8:
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case MVT::v8i16:
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case MVT::v4i32:
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case MVT::v2i64:
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case MVT::v4f32:
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case MVT::v2f64: {
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Reg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs], X86::VR128RegisterClass);
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ArgValue = DAG.getCopyFromReg(Root, Reg, ObjectVT);
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break;
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}
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}
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NumIntRegs += ObjIntRegs;
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NumXMMRegs += ObjXMMRegs;
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}
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if (ObjSize) {
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// XMM arguments have to be aligned on 16-byte boundary.
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if (ObjSize == 16)
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ArgOffset = ((ArgOffset + 15) / 16) * 16;
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// Create the SelectionDAG nodes corresponding to a load from this
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// parameter.
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int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
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SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
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ArgValue = DAG.getLoad(Op.Val->getValueType(i), Root, FIN, NULL, 0);
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ArgOffset += ArgIncrement; // Move on to the next argument.
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}
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ArgValues.push_back(ArgValue);
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(MF.getFunction()->getCallingConv(), getTargetMachine(),
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ArgLocs);
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for (unsigned i = 0; i != NumArgs; ++i) {
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MVT::ValueType ArgVT = Op.getValue(i).getValueType();
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unsigned ArgFlags = cast<ConstantSDNode>(Op.getOperand(3+i))->getValue();
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if (CC_X86_32_FastCall(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,CCInfo))
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assert(0 && "Unhandled argument type!");
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}
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SmallVector<SDOperand, 8> ArgValues;
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unsigned LastVal = ~0U;
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for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
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CCValAssign &VA = ArgLocs[i];
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// TODO: If an arg is passed in two places (e.g. reg and stack), skip later
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// places.
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assert(VA.getValNo() != LastVal &&
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"Don't support value assigned to multiple locs yet");
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LastVal = VA.getValNo();
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if (VA.isRegLoc()) {
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MVT::ValueType RegVT = VA.getLocVT();
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TargetRegisterClass *RC;
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if (RegVT == MVT::i32)
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RC = X86::GR32RegisterClass;
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else {
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assert(MVT::isVector(RegVT));
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RC = X86::VR128RegisterClass;
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}
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SDOperand ArgValue = DAG.getCopyFromReg(Root, VA.getLocReg(), RegVT);
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AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
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// If this is an 8 or 16-bit value, it is really passed promoted to 32
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// bits. Insert an assert[sz]ext to capture this, then truncate to the
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// right size.
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if (VA.getLocInfo() == CCValAssign::SExt)
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ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
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DAG.getValueType(VA.getValVT()));
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else if (VA.getLocInfo() == CCValAssign::ZExt)
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ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
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DAG.getValueType(VA.getValVT()));
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if (VA.getLocInfo() != CCValAssign::Full)
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ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
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ArgValues.push_back(ArgValue);
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} else {
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assert(VA.isMemLoc());
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// Create the nodes corresponding to a load from this parameter slot.
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int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8,
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VA.getLocMemOffset());
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SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
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ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0));
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}
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}
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ArgValues.push_back(Root);
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unsigned StackSize = CCInfo.getNextStackOffset();
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// Make sure the instruction takes 8n+4 bytes to make sure the start of the
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// arguments and the arguments after the retaddr has been pushed are aligned.
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if ((ArgOffset & 7) == 0)
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ArgOffset += 4;
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if ((StackSize & 7) == 0)
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StackSize += 4;
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VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
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RegSaveFrameIndex = 0xAAAAAAA; // X86-64 only.
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ReturnAddrIndex = 0; // No return address slot generated yet.
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BytesToPopOnReturn = ArgOffset; // Callee pops all stack arguments.
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BytesToPopOnReturn = StackSize; // Callee pops all stack arguments.
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BytesCallerReserves = 0;
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MF.getInfo<X86FunctionInfo>()->setBytesToPopOnReturn(BytesToPopOnReturn);
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// Finally, inform the code generator which regs we return values in.
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switch (getValueType(MF.getFunction()->getReturnType())) {
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default: assert(0 && "Unknown type!");
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case MVT::isVoid: break;
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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MF.addLiveOut(X86::EAX);
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break;
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case MVT::i64:
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MF.addLiveOut(X86::EAX);
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MF.addLiveOut(X86::EDX);
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break;
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case MVT::f32:
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case MVT::f64:
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MF.addLiveOut(X86::ST0);
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break;
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case MVT::v16i8:
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case MVT::v8i16:
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case MVT::v4i32:
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case MVT::v2i64:
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case MVT::v4f32:
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case MVT::v2f64:
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MF.addLiveOut(X86::XMM0);
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break;
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}
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// Return the new list of results.
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return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
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&ArgValues[0], ArgValues.size()).getValue(Op.ResNo);
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