mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-19 17:33:29 +00:00
Move more code around and duplicate AVX patterns: MOVHPS and MOVLPS
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138897 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes
parent
06c982d0e0
commit
fc7bc5889b
@ -783,9 +783,8 @@ let Predicates = [HasAVX] in {
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(VMOVUPSYmr addr:$dst, VR256:$src)>;
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}
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//===----------------------------------------------------------------------===//
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// SSE 1 & 2 - Move Low/High packed FP Instructions
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// SSE 1 & 2 - Move Low packed FP Instructions
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//===----------------------------------------------------------------------===//
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multiclass sse12_mov_hilo_packed<bits<8>opc, RegisterClass RC,
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@ -810,14 +809,10 @@ multiclass sse12_mov_hilo_packed<bits<8>opc, RegisterClass RC,
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let AddedComplexity = 20 in {
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defm VMOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
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"\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
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defm VMOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
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"\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
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}
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let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
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defm MOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
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"\t{$src2, $dst|$dst, $src2}">;
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defm MOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
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"\t{$src2, $dst|$dst, $src2}">;
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}
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def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
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@ -837,6 +832,147 @@ def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
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[(store (f64 (vector_extract (v2f64 VR128:$src),
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(iPTR 0))), addr:$dst)]>;
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let Predicates = [HasAVX] in {
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let AddedComplexity = 20 in {
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// vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
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def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
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(VMOVLPSrm VR128:$src1, addr:$src2)>;
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def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
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(VMOVLPSrm VR128:$src1, addr:$src2)>;
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// vector_shuffle v1, (load v2) <2, 1> using MOVLPS
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def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
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(VMOVLPDrm VR128:$src1, addr:$src2)>;
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def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
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(VMOVLPDrm VR128:$src1, addr:$src2)>;
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}
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// (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
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def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
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(VMOVLPSmr addr:$src1, VR128:$src2)>;
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def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)),
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VR128:$src2)), addr:$src1),
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(VMOVLPSmr addr:$src1, VR128:$src2)>;
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// (store (vector_shuffle (load addr), v2, <2, 1>), addr) using MOVLPS
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def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
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(VMOVLPDmr addr:$src1, VR128:$src2)>;
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def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
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(VMOVLPDmr addr:$src1, VR128:$src2)>;
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// Shuffle with VMOVLPS
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def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
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(VMOVLPSrm VR128:$src1, addr:$src2)>;
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def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
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(VMOVLPSrm VR128:$src1, addr:$src2)>;
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def : Pat<(X86Movlps VR128:$src1,
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(bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
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(VMOVLPSrm VR128:$src1, addr:$src2)>;
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// Shuffle with VMOVLPD
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def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
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(VMOVLPDrm VR128:$src1, addr:$src2)>;
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def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
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(VMOVLPDrm VR128:$src1, addr:$src2)>;
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def : Pat<(v2f64 (X86Movlpd VR128:$src1,
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(scalar_to_vector (loadf64 addr:$src2)))),
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(VMOVLPDrm VR128:$src1, addr:$src2)>;
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// Store patterns
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def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
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addr:$src1),
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(VMOVLPSmr addr:$src1, VR128:$src2)>;
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def : Pat<(store (v4i32 (X86Movlps
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(bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
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(VMOVLPSmr addr:$src1, VR128:$src2)>;
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def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
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addr:$src1),
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(VMOVLPDmr addr:$src1, VR128:$src2)>;
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def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
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addr:$src1),
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(VMOVLPDmr addr:$src1, VR128:$src2)>;
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}
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let Predicates = [HasSSE1] in {
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let AddedComplexity = 20 in {
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// vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
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def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
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(MOVLPSrm VR128:$src1, addr:$src2)>;
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def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
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(MOVLPSrm VR128:$src1, addr:$src2)>;
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}
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// (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
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def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
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(MOVLPSmr addr:$src1, VR128:$src2)>;
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def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)),
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VR128:$src2)), addr:$src1),
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(MOVLPSmr addr:$src1, VR128:$src2)>;
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// Shuffle with MOVLPS
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def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
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(MOVLPSrm VR128:$src1, addr:$src2)>;
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def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
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(MOVLPSrm VR128:$src1, addr:$src2)>;
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def : Pat<(X86Movlps VR128:$src1,
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(bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
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(MOVLPSrm VR128:$src1, addr:$src2)>;
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// Store patterns
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def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
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addr:$src1),
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(MOVLPSmr addr:$src1, VR128:$src2)>;
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def : Pat<(store (v4i32 (X86Movlps
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(bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
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addr:$src1),
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(MOVLPSmr addr:$src1, VR128:$src2)>;
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}
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let Predicates = [HasSSE2] in {
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let AddedComplexity = 20 in {
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// vector_shuffle v1, (load v2) <2, 1> using MOVLPS
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def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
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(MOVLPDrm VR128:$src1, addr:$src2)>;
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def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
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(MOVLPDrm VR128:$src1, addr:$src2)>;
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}
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// (store (vector_shuffle (load addr), v2, <2, 1>), addr) using MOVLPS
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def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
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(MOVLPDmr addr:$src1, VR128:$src2)>;
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def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
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(MOVLPDmr addr:$src1, VR128:$src2)>;
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// Shuffle with MOVLPD
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def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
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(MOVLPDrm VR128:$src1, addr:$src2)>;
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def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
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(MOVLPDrm VR128:$src1, addr:$src2)>;
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def : Pat<(v2f64 (X86Movlpd VR128:$src1,
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(scalar_to_vector (loadf64 addr:$src2)))),
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(MOVLPDrm VR128:$src1, addr:$src2)>;
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// Store patterns
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def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
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addr:$src1),
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(MOVLPDmr addr:$src1, VR128:$src2)>;
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def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
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addr:$src1),
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(MOVLPDmr addr:$src1, VR128:$src2)>;
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}
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//===----------------------------------------------------------------------===//
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// SSE 1 & 2 - Move Hi packed FP Instructions
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//===----------------------------------------------------------------------===//
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let AddedComplexity = 20 in {
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defm VMOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
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"\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
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}
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let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
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defm MOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
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"\t{$src2, $dst|$dst, $src2}">;
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}
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// v2f64 extract element 1 is always custom lowered to unpack high to low
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// and extract element 0 so the non-store version isn't too horrible.
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def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
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@ -862,6 +998,80 @@ def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
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(v2f64 (unpckh VR128:$src, (undef))),
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(iPTR 0))), addr:$dst)]>;
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let Predicates = [HasAVX] in {
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// VMOVHPS patterns
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def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
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(VMOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
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def : Pat<(X86Movlhps VR128:$src1,
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(bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
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(VMOVHPSrm VR128:$src1, addr:$src2)>;
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def : Pat<(X86Movlhps VR128:$src1,
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(bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
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(VMOVHPSrm VR128:$src1, addr:$src2)>;
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// FIXME: Instead of X86Unpcklpd, there should be a X86Movlhpd here, the problem
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// is during lowering, where it's not possible to recognize the load fold cause
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// it has two uses through a bitcast. One use disappears at isel time and the
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// fold opportunity reappears.
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def : Pat<(v2f64 (X86Unpcklpd VR128:$src1,
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(scalar_to_vector (loadf64 addr:$src2)))),
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(VMOVHPDrm VR128:$src1, addr:$src2)>;
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// FIXME: This should be matched by a X86Movhpd instead. Same as above
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def : Pat<(v2f64 (X86Movlhpd VR128:$src1,
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(scalar_to_vector (loadf64 addr:$src2)))),
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(VMOVHPDrm VR128:$src1, addr:$src2)>;
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// Store patterns
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def : Pat<(store (f64 (vector_extract
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(v2f64 (X86Unpckhps VR128:$src, (undef))), (iPTR 0))), addr:$dst),
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(VMOVHPSmr addr:$dst, VR128:$src)>;
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def : Pat<(store (f64 (vector_extract
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(v2f64 (X86Unpckhpd VR128:$src, (undef))), (iPTR 0))), addr:$dst),
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(VMOVHPDmr addr:$dst, VR128:$src)>;
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}
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let Predicates = [HasSSE1] in {
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// MOVHPS patterns
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def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
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(MOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
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def : Pat<(X86Movlhps VR128:$src1,
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(bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
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(MOVHPSrm VR128:$src1, addr:$src2)>;
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def : Pat<(X86Movlhps VR128:$src1,
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(bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
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(MOVHPSrm VR128:$src1, addr:$src2)>;
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// Store patterns
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def : Pat<(store (f64 (vector_extract
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(v2f64 (X86Unpckhps VR128:$src, (undef))), (iPTR 0))), addr:$dst),
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(MOVHPSmr addr:$dst, VR128:$src)>;
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}
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let Predicates = [HasSSE2] in {
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// FIXME: Instead of X86Unpcklpd, there should be a X86Movlhpd here, the problem
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// is during lowering, where it's not possible to recognize the load fold cause
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// it has two uses through a bitcast. One use disappears at isel time and the
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// fold opportunity reappears.
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def : Pat<(v2f64 (X86Unpcklpd VR128:$src1,
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(scalar_to_vector (loadf64 addr:$src2)))),
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(MOVHPDrm VR128:$src1, addr:$src2)>;
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// FIXME: This should be matched by a X86Movhpd instead. Same as above
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def : Pat<(v2f64 (X86Movlhpd VR128:$src1,
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(scalar_to_vector (loadf64 addr:$src2)))),
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(MOVHPDrm VR128:$src1, addr:$src2)>;
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// Store patterns
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def : Pat<(store (f64 (vector_extract
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(v2f64 (X86Unpckhpd VR128:$src, (undef))), (iPTR 0))),addr:$dst),
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(MOVHPDmr addr:$dst, VR128:$src)>;
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}
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//===----------------------------------------------------------------------===//
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// SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
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//===----------------------------------------------------------------------===//
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let AddedComplexity = 20 in {
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def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2),
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@ -890,16 +1100,6 @@ let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
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}
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let Predicates = [HasAVX] in {
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// MOVHPS patterns
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def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
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(VMOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
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def : Pat<(X86Movlhps VR128:$src1,
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(bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
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(VMOVHPSrm VR128:$src1, addr:$src2)>;
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def : Pat<(X86Movlhps VR128:$src1,
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(bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
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(VMOVHPSrm VR128:$src1, addr:$src2)>;
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// MOVLHPS patterns
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let AddedComplexity = 20 in {
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def : Pat<(v4f32 (movddup VR128:$src, (undef))),
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@ -938,17 +1138,6 @@ let Predicates = [HasAVX] in {
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}
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let Predicates = [HasSSE1] in {
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// MOVHPS patterns
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def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
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(MOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
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def : Pat<(X86Movlhps VR128:$src1,
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(bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
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(MOVHPSrm VR128:$src1, addr:$src2)>;
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def : Pat<(X86Movlhps VR128:$src1,
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(bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
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(MOVHPSrm VR128:$src1, addr:$src2)>;
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// MOVLHPS patterns
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let AddedComplexity = 20 in {
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def : Pat<(v4f32 (movddup VR128:$src, (undef))),
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@ -4648,29 +4837,6 @@ def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
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(PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
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}
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let AddedComplexity = 20 in {
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// vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
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def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
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(MOVLPSrm VR128:$src1, addr:$src2)>;
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def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
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(MOVLPDrm VR128:$src1, addr:$src2)>;
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def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
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(MOVLPSrm VR128:$src1, addr:$src2)>;
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def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
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(MOVLPDrm VR128:$src1, addr:$src2)>;
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}
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// (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
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def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
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(MOVLPSmr addr:$src1, VR128:$src2)>;
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def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
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(MOVLPDmr addr:$src1, VR128:$src2)>;
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def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
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addr:$src1),
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(MOVLPSmr addr:$src1, VR128:$src2)>;
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def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
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(MOVLPDmr addr:$src1, VR128:$src2)>;
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// Set lowest element and zero upper elements.
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def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
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(MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
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@ -6306,62 +6472,3 @@ let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
|
||||
[(int_x86_avx_vzeroupper)]>, TB, VEX, Requires<[HasAVX]>;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// SSE Shuffle pattern fragments
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// This is part of a "work in progress" refactoring. The idea is that all
|
||||
// vector shuffles are going to be translated into target specific nodes and
|
||||
// directly matched by the patterns below (which can be changed along the way)
|
||||
// The AVX version of some but not all of them are described here, and more
|
||||
// should come in a near future.
|
||||
|
||||
// Shuffle with MOVLHPD
|
||||
def : Pat<(v2f64 (X86Movlhpd VR128:$src1,
|
||||
(scalar_to_vector (loadf64 addr:$src2)))),
|
||||
(MOVHPDrm VR128:$src1, addr:$src2)>;
|
||||
|
||||
// FIXME: Instead of X86Unpcklpd, there should be a X86Movlhpd here, the problem
|
||||
// is during lowering, where it's not possible to recognize the load fold cause
|
||||
// it has two uses through a bitcast. One use disappears at isel time and the
|
||||
// fold opportunity reappears.
|
||||
def : Pat<(v2f64 (X86Unpcklpd VR128:$src1,
|
||||
(scalar_to_vector (loadf64 addr:$src2)))),
|
||||
(MOVHPDrm VR128:$src1, addr:$src2)>;
|
||||
|
||||
// Shuffle with MOVLPS
|
||||
def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
|
||||
(MOVLPSrm VR128:$src1, addr:$src2)>;
|
||||
def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
|
||||
(MOVLPSrm VR128:$src1, addr:$src2)>;
|
||||
def : Pat<(X86Movlps VR128:$src1,
|
||||
(bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
|
||||
(MOVLPSrm VR128:$src1, addr:$src2)>;
|
||||
|
||||
// Shuffle with MOVLPD
|
||||
def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
|
||||
(MOVLPDrm VR128:$src1, addr:$src2)>;
|
||||
def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
|
||||
(MOVLPDrm VR128:$src1, addr:$src2)>;
|
||||
def : Pat<(v2f64 (X86Movlpd VR128:$src1,
|
||||
(scalar_to_vector (loadf64 addr:$src2)))),
|
||||
(MOVLPDrm VR128:$src1, addr:$src2)>;
|
||||
|
||||
// Extra patterns to match stores with MOVHPS/PD and MOVLPS/PD
|
||||
def : Pat<(store (f64 (vector_extract
|
||||
(v2f64 (X86Unpckhps VR128:$src, (undef))), (iPTR 0))),addr:$dst),
|
||||
(MOVHPSmr addr:$dst, VR128:$src)>;
|
||||
def : Pat<(store (f64 (vector_extract
|
||||
(v2f64 (X86Unpckhpd VR128:$src, (undef))), (iPTR 0))),addr:$dst),
|
||||
(MOVHPDmr addr:$dst, VR128:$src)>;
|
||||
|
||||
def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),addr:$src1),
|
||||
(MOVLPSmr addr:$src1, VR128:$src2)>;
|
||||
def : Pat<(store (v4i32 (X86Movlps
|
||||
(bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
|
||||
(MOVLPSmr addr:$src1, VR128:$src2)>;
|
||||
|
||||
def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),addr:$src1),
|
||||
(MOVLPDmr addr:$src1, VR128:$src2)>;
|
||||
def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),addr:$src1),
|
||||
(MOVLPDmr addr:$src1, VR128:$src2)>;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user