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[Sparc] Add support for parsing floating point instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199033 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Venkatraman Govindaraju
@@ -601,164 +601,164 @@ let Defs = [Y], rd = 0 in {
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}
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// Convert Integer to Floating-point Instructions, p. 141
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def FITOS : F3_3u<2, 0b110100, 0b011000100,
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(outs FPRegs:$dst), (ins FPRegs:$src),
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"fitos $src, $dst",
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[(set FPRegs:$dst, (SPitof FPRegs:$src))]>;
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(outs FPRegs:$rd), (ins FPRegs:$rs2),
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"fitos $rs2, $rd",
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[(set FPRegs:$rd, (SPitof FPRegs:$rs2))]>;
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def FITOD : F3_3u<2, 0b110100, 0b011001000,
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(outs DFPRegs:$dst), (ins FPRegs:$src),
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"fitod $src, $dst",
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[(set DFPRegs:$dst, (SPitof FPRegs:$src))]>;
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(outs DFPRegs:$rd), (ins FPRegs:$rs2),
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"fitod $rs2, $rd",
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[(set DFPRegs:$rd, (SPitof FPRegs:$rs2))]>;
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def FITOQ : F3_3u<2, 0b110100, 0b011001100,
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(outs QFPRegs:$dst), (ins FPRegs:$src),
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"fitoq $src, $dst",
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[(set QFPRegs:$dst, (SPitof FPRegs:$src))]>,
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(outs QFPRegs:$rd), (ins FPRegs:$rs2),
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"fitoq $rs2, $rd",
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[(set QFPRegs:$rd, (SPitof FPRegs:$rs2))]>,
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Requires<[HasHardQuad]>;
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// Convert Floating-point to Integer Instructions, p. 142
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def FSTOI : F3_3u<2, 0b110100, 0b011010001,
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(outs FPRegs:$dst), (ins FPRegs:$src),
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"fstoi $src, $dst",
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[(set FPRegs:$dst, (SPftoi FPRegs:$src))]>;
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(outs FPRegs:$rd), (ins FPRegs:$rs2),
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"fstoi $rs2, $rd",
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[(set FPRegs:$rd, (SPftoi FPRegs:$rs2))]>;
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def FDTOI : F3_3u<2, 0b110100, 0b011010010,
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(outs FPRegs:$dst), (ins DFPRegs:$src),
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"fdtoi $src, $dst",
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[(set FPRegs:$dst, (SPftoi DFPRegs:$src))]>;
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(outs FPRegs:$rd), (ins DFPRegs:$rs2),
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"fdtoi $rs2, $rd",
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[(set FPRegs:$rd, (SPftoi DFPRegs:$rs2))]>;
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def FQTOI : F3_3u<2, 0b110100, 0b011010011,
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(outs FPRegs:$dst), (ins QFPRegs:$src),
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"fqtoi $src, $dst",
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[(set FPRegs:$dst, (SPftoi QFPRegs:$src))]>,
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(outs FPRegs:$rd), (ins QFPRegs:$rs2),
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"fqtoi $rs2, $rd",
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[(set FPRegs:$rd, (SPftoi QFPRegs:$rs2))]>,
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Requires<[HasHardQuad]>;
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// Convert between Floating-point Formats Instructions, p. 143
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def FSTOD : F3_3u<2, 0b110100, 0b011001001,
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(outs DFPRegs:$dst), (ins FPRegs:$src),
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"fstod $src, $dst",
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[(set f64:$dst, (fextend f32:$src))]>;
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(outs DFPRegs:$rd), (ins FPRegs:$rs2),
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"fstod $rs2, $rd",
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[(set f64:$rd, (fextend f32:$rs2))]>;
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def FSTOQ : F3_3u<2, 0b110100, 0b011001101,
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(outs QFPRegs:$dst), (ins FPRegs:$src),
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"fstoq $src, $dst",
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[(set f128:$dst, (fextend f32:$src))]>,
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(outs QFPRegs:$rd), (ins FPRegs:$rs2),
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"fstoq $rs2, $rd",
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[(set f128:$rd, (fextend f32:$rs2))]>,
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Requires<[HasHardQuad]>;
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def FDTOS : F3_3u<2, 0b110100, 0b011000110,
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(outs FPRegs:$dst), (ins DFPRegs:$src),
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"fdtos $src, $dst",
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[(set f32:$dst, (fround f64:$src))]>;
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def FDTOQ : F3_3u<2, 0b110100, 0b01101110,
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(outs QFPRegs:$dst), (ins DFPRegs:$src),
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"fdtoq $src, $dst",
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[(set f128:$dst, (fextend f64:$src))]>,
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(outs FPRegs:$rd), (ins DFPRegs:$rs2),
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"fdtos $rs2, $rd",
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[(set f32:$rd, (fround f64:$rs2))]>;
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def FDTOQ : F3_3u<2, 0b110100, 0b011001110,
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(outs QFPRegs:$rd), (ins DFPRegs:$rs2),
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"fdtoq $rs2, $rd",
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[(set f128:$rd, (fextend f64:$rs2))]>,
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Requires<[HasHardQuad]>;
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def FQTOS : F3_3u<2, 0b110100, 0b011000111,
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(outs FPRegs:$dst), (ins QFPRegs:$src),
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"fqtos $src, $dst",
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[(set f32:$dst, (fround f128:$src))]>,
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(outs FPRegs:$rd), (ins QFPRegs:$rs2),
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"fqtos $rs2, $rd",
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[(set f32:$rd, (fround f128:$rs2))]>,
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Requires<[HasHardQuad]>;
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def FQTOD : F3_3u<2, 0b110100, 0b011001011,
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(outs DFPRegs:$dst), (ins QFPRegs:$src),
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"fqtod $src, $dst",
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[(set f64:$dst, (fround f128:$src))]>,
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(outs DFPRegs:$rd), (ins QFPRegs:$rs2),
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"fqtod $rs2, $rd",
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[(set f64:$rd, (fround f128:$rs2))]>,
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Requires<[HasHardQuad]>;
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// Floating-point Move Instructions, p. 144
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def FMOVS : F3_3u<2, 0b110100, 0b000000001,
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(outs FPRegs:$dst), (ins FPRegs:$src),
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"fmovs $src, $dst", []>;
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(outs FPRegs:$rd), (ins FPRegs:$rs2),
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"fmovs $rs2, $rd", []>;
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def FNEGS : F3_3u<2, 0b110100, 0b000000101,
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(outs FPRegs:$dst), (ins FPRegs:$src),
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"fnegs $src, $dst",
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[(set f32:$dst, (fneg f32:$src))]>;
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(outs FPRegs:$rd), (ins FPRegs:$rs2),
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"fnegs $rs2, $rd",
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[(set f32:$rd, (fneg f32:$rs2))]>;
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def FABSS : F3_3u<2, 0b110100, 0b000001001,
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(outs FPRegs:$dst), (ins FPRegs:$src),
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"fabss $src, $dst",
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[(set f32:$dst, (fabs f32:$src))]>;
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(outs FPRegs:$rd), (ins FPRegs:$rs2),
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"fabss $rs2, $rd",
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[(set f32:$rd, (fabs f32:$rs2))]>;
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// Floating-point Square Root Instructions, p.145
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def FSQRTS : F3_3u<2, 0b110100, 0b000101001,
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(outs FPRegs:$dst), (ins FPRegs:$src),
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"fsqrts $src, $dst",
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[(set f32:$dst, (fsqrt f32:$src))]>;
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(outs FPRegs:$rd), (ins FPRegs:$rs2),
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"fsqrts $rs2, $rd",
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[(set f32:$rd, (fsqrt f32:$rs2))]>;
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def FSQRTD : F3_3u<2, 0b110100, 0b000101010,
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(outs DFPRegs:$dst), (ins DFPRegs:$src),
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"fsqrtd $src, $dst",
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[(set f64:$dst, (fsqrt f64:$src))]>;
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(outs DFPRegs:$rd), (ins DFPRegs:$rs2),
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"fsqrtd $rs2, $rd",
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[(set f64:$rd, (fsqrt f64:$rs2))]>;
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def FSQRTQ : F3_3u<2, 0b110100, 0b000101011,
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(outs QFPRegs:$dst), (ins QFPRegs:$src),
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"fsqrtq $src, $dst",
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[(set f128:$dst, (fsqrt f128:$src))]>,
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(outs QFPRegs:$rd), (ins QFPRegs:$rs2),
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"fsqrtq $rs2, $rd",
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[(set f128:$rd, (fsqrt f128:$rs2))]>,
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Requires<[HasHardQuad]>;
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// Floating-point Add and Subtract Instructions, p. 146
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def FADDS : F3_3<2, 0b110100, 0b001000001,
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(outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
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"fadds $src1, $src2, $dst",
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[(set f32:$dst, (fadd f32:$src1, f32:$src2))]>;
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(outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
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"fadds $rs1, $rs2, $rd",
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[(set f32:$rd, (fadd f32:$rs1, f32:$rs2))]>;
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def FADDD : F3_3<2, 0b110100, 0b001000010,
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(outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
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"faddd $src1, $src2, $dst",
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[(set f64:$dst, (fadd f64:$src1, f64:$src2))]>;
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(outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
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"faddd $rs1, $rs2, $rd",
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[(set f64:$rd, (fadd f64:$rs1, f64:$rs2))]>;
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def FADDQ : F3_3<2, 0b110100, 0b001000011,
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(outs QFPRegs:$dst), (ins QFPRegs:$src1, QFPRegs:$src2),
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"faddq $src1, $src2, $dst",
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[(set f128:$dst, (fadd f128:$src1, f128:$src2))]>,
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(outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
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"faddq $rs1, $rs2, $rd",
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[(set f128:$rd, (fadd f128:$rs1, f128:$rs2))]>,
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Requires<[HasHardQuad]>;
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def FSUBS : F3_3<2, 0b110100, 0b001000101,
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(outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
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"fsubs $src1, $src2, $dst",
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[(set f32:$dst, (fsub f32:$src1, f32:$src2))]>;
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(outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
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"fsubs $rs1, $rs2, $rd",
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[(set f32:$rd, (fsub f32:$rs1, f32:$rs2))]>;
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def FSUBD : F3_3<2, 0b110100, 0b001000110,
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(outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
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"fsubd $src1, $src2, $dst",
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[(set f64:$dst, (fsub f64:$src1, f64:$src2))]>;
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(outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
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"fsubd $rs1, $rs2, $rd",
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[(set f64:$rd, (fsub f64:$rs1, f64:$rs2))]>;
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def FSUBQ : F3_3<2, 0b110100, 0b001000111,
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(outs QFPRegs:$dst), (ins QFPRegs:$src1, QFPRegs:$src2),
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"fsubq $src1, $src2, $dst",
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[(set f128:$dst, (fsub f128:$src1, f128:$src2))]>,
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(outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
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"fsubq $rs1, $rs2, $rd",
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[(set f128:$rd, (fsub f128:$rs1, f128:$rs2))]>,
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Requires<[HasHardQuad]>;
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// Floating-point Multiply and Divide Instructions, p. 147
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def FMULS : F3_3<2, 0b110100, 0b001001001,
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(outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
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"fmuls $src1, $src2, $dst",
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[(set f32:$dst, (fmul f32:$src1, f32:$src2))]>;
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(outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
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"fmuls $rs1, $rs2, $rd",
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[(set f32:$rd, (fmul f32:$rs1, f32:$rs2))]>;
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def FMULD : F3_3<2, 0b110100, 0b001001010,
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(outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
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"fmuld $src1, $src2, $dst",
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[(set f64:$dst, (fmul f64:$src1, f64:$src2))]>;
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(outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
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"fmuld $rs1, $rs2, $rd",
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[(set f64:$rd, (fmul f64:$rs1, f64:$rs2))]>;
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def FMULQ : F3_3<2, 0b110100, 0b001001011,
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(outs QFPRegs:$dst), (ins QFPRegs:$src1, QFPRegs:$src2),
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"fmulq $src1, $src2, $dst",
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[(set f128:$dst, (fmul f128:$src1, f128:$src2))]>,
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(outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
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"fmulq $rs1, $rs2, $rd",
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[(set f128:$rd, (fmul f128:$rs1, f128:$rs2))]>,
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Requires<[HasHardQuad]>;
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def FSMULD : F3_3<2, 0b110100, 0b001101001,
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(outs DFPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
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"fsmuld $src1, $src2, $dst",
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[(set f64:$dst, (fmul (fextend f32:$src1),
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(fextend f32:$src2)))]>;
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(outs DFPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
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"fsmuld $rs1, $rs2, $rd",
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[(set f64:$rd, (fmul (fextend f32:$rs1),
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(fextend f32:$rs2)))]>;
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def FDMULQ : F3_3<2, 0b110100, 0b001101110,
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(outs QFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
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"fdmulq $src1, $src2, $dst",
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[(set f128:$dst, (fmul (fextend f64:$src1),
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(fextend f64:$src2)))]>,
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(outs QFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
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"fdmulq $rs1, $rs2, $rd",
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[(set f128:$rd, (fmul (fextend f64:$rs1),
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(fextend f64:$rs2)))]>,
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Requires<[HasHardQuad]>;
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def FDIVS : F3_3<2, 0b110100, 0b001001101,
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(outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
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"fdivs $src1, $src2, $dst",
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[(set f32:$dst, (fdiv f32:$src1, f32:$src2))]>;
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(outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
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"fdivs $rs1, $rs2, $rd",
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[(set f32:$rd, (fdiv f32:$rs1, f32:$rs2))]>;
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def FDIVD : F3_3<2, 0b110100, 0b001001110,
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(outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
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"fdivd $src1, $src2, $dst",
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[(set f64:$dst, (fdiv f64:$src1, f64:$src2))]>;
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(outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
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"fdivd $rs1, $rs2, $rd",
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[(set f64:$rd, (fdiv f64:$rs1, f64:$rs2))]>;
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def FDIVQ : F3_3<2, 0b110100, 0b001001111,
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(outs QFPRegs:$dst), (ins QFPRegs:$src1, QFPRegs:$src2),
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"fdivq $src1, $src2, $dst",
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[(set f128:$dst, (fdiv f128:$src1, f128:$src2))]>,
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(outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
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"fdivq $rs1, $rs2, $rd",
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[(set f128:$rd, (fdiv f128:$rs1, f128:$rs2))]>,
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Requires<[HasHardQuad]>;
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// Floating-point Compare Instructions, p. 148
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@@ -770,17 +770,17 @@ def FDIVQ : F3_3<2, 0b110100, 0b001001111,
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let Defs = [FCC] in {
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def FCMPS : F3_3c<2, 0b110101, 0b001010001,
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(outs), (ins FPRegs:$src1, FPRegs:$src2),
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"fcmps $src1, $src2",
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[(SPcmpfcc f32:$src1, f32:$src2)]>;
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(outs), (ins FPRegs:$rs1, FPRegs:$rs2),
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"fcmps $rs1, $rs2",
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[(SPcmpfcc f32:$rs1, f32:$rs2)]>;
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def FCMPD : F3_3c<2, 0b110101, 0b001010010,
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(outs), (ins DFPRegs:$src1, DFPRegs:$src2),
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"fcmpd $src1, $src2",
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[(SPcmpfcc f64:$src1, f64:$src2)]>;
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(outs), (ins DFPRegs:$rs1, DFPRegs:$rs2),
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"fcmpd $rs1, $rs2",
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[(SPcmpfcc f64:$rs1, f64:$rs2)]>;
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def FCMPQ : F3_3c<2, 0b110101, 0b001010011,
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(outs), (ins QFPRegs:$src1, QFPRegs:$src2),
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"fcmpq $src1, $src2",
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[(SPcmpfcc f128:$src1, f128:$src2)]>,
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(outs), (ins QFPRegs:$rs1, QFPRegs:$rs2),
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"fcmpq $rs1, $rs2",
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[(SPcmpfcc f128:$rs1, f128:$rs2)]>,
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Requires<[HasHardQuad]>;
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}
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@@ -892,29 +892,29 @@ let Predicates = [HasV9], Constraints = "$f = $rd" in {
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// Floating-Point Move Instructions, p. 164 of the V9 manual.
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let Predicates = [HasV9] in {
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def FMOVD : F3_3u<2, 0b110100, 0b000000010,
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(outs DFPRegs:$dst), (ins DFPRegs:$src),
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"fmovd $src, $dst", []>;
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(outs DFPRegs:$rd), (ins DFPRegs:$rs2),
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"fmovd $rs2, $rd", []>;
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def FMOVQ : F3_3u<2, 0b110100, 0b000000011,
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(outs QFPRegs:$dst), (ins QFPRegs:$src),
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"fmovq $src, $dst", []>,
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(outs QFPRegs:$rd), (ins QFPRegs:$rs2),
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"fmovq $rs2, $rd", []>,
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Requires<[HasHardQuad]>;
|
||||
def FNEGD : F3_3u<2, 0b110100, 0b000000110,
|
||||
(outs DFPRegs:$dst), (ins DFPRegs:$src),
|
||||
"fnegd $src, $dst",
|
||||
[(set f64:$dst, (fneg f64:$src))]>;
|
||||
(outs DFPRegs:$rd), (ins DFPRegs:$rs2),
|
||||
"fnegd $rs2, $rd",
|
||||
[(set f64:$rd, (fneg f64:$rs2))]>;
|
||||
def FNEGQ : F3_3u<2, 0b110100, 0b000000111,
|
||||
(outs QFPRegs:$dst), (ins QFPRegs:$src),
|
||||
"fnegq $src, $dst",
|
||||
[(set f128:$dst, (fneg f128:$src))]>,
|
||||
(outs QFPRegs:$rd), (ins QFPRegs:$rs2),
|
||||
"fnegq $rs2, $rd",
|
||||
[(set f128:$rd, (fneg f128:$rs2))]>,
|
||||
Requires<[HasHardQuad]>;
|
||||
def FABSD : F3_3u<2, 0b110100, 0b000001010,
|
||||
(outs DFPRegs:$dst), (ins DFPRegs:$src),
|
||||
"fabsd $src, $dst",
|
||||
[(set f64:$dst, (fabs f64:$src))]>;
|
||||
(outs DFPRegs:$rd), (ins DFPRegs:$rs2),
|
||||
"fabsd $rs2, $rd",
|
||||
[(set f64:$rd, (fabs f64:$rs2))]>;
|
||||
def FABSQ : F3_3u<2, 0b110100, 0b000001011,
|
||||
(outs QFPRegs:$dst), (ins QFPRegs:$src),
|
||||
"fabsq $src, $dst",
|
||||
[(set f128:$dst, (fabs f128:$src))]>,
|
||||
(outs QFPRegs:$rd), (ins QFPRegs:$rs2),
|
||||
"fabsq $rs2, $rd",
|
||||
[(set f128:$rd, (fabs f128:$rs2))]>,
|
||||
Requires<[HasHardQuad]>;
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user