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Fixes win64. It was broken by a previous patch where I missed the !isWin64

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and then forced every register to be a vr128 on win64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109060 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Rafael Espindola 2010-07-21 23:19:57 +00:00
parent d8cc7be026
commit fcbd1a749f
1 changed files with 8 additions and 4 deletions
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12
lib/Target/X86/X86InstrInfo.cpp
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@ -2062,6 +2062,7 @@ bool X86InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
DebugLoc DL = MBB.findDebugLoc(MI); DebugLoc DL = MBB.findDebugLoc(MI);
bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit(); bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
bool isWin64 = TM.getSubtarget<X86Subtarget>().isTargetWin64();
unsigned SlotSize = is64Bit ? 8 : 4; unsigned SlotSize = is64Bit ? 8 : 4;
MachineFunction &MF = *MBB.getParent(); MachineFunction &MF = *MBB.getParent();
@ -2077,12 +2078,13 @@ bool X86InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
if (Reg == FPReg) if (Reg == FPReg)
// X86RegisterInfo::emitPrologue will handle spilling of frame register. // X86RegisterInfo::emitPrologue will handle spilling of frame register.
continue; continue;
if (!X86::VR128RegClass.contains(Reg)) { if (!X86::VR128RegClass.contains(Reg) && !isWin64) {
CalleeFrameSize += SlotSize; CalleeFrameSize += SlotSize;
BuildMI(MBB, MI, DL, get(Opc)).addReg(Reg, RegState::Kill); BuildMI(MBB, MI, DL, get(Opc)).addReg(Reg, RegState::Kill);
} else { } else {
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
storeRegToStackSlot(MBB, MI, Reg, true, CSI[i-1].getFrameIdx(), storeRegToStackSlot(MBB, MI, Reg, true, CSI[i-1].getFrameIdx(),
&X86::VR128RegClass, &RI); RC, &RI);
} }
} }
@ -2102,17 +2104,19 @@ bool X86InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
MachineFunction &MF = *MBB.getParent(); MachineFunction &MF = *MBB.getParent();
unsigned FPReg = RI.getFrameRegister(MF); unsigned FPReg = RI.getFrameRegister(MF);
bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit(); bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
bool isWin64 = TM.getSubtarget<X86Subtarget>().isTargetWin64();
unsigned Opc = is64Bit ? X86::POP64r : X86::POP32r; unsigned Opc = is64Bit ? X86::POP64r : X86::POP32r;
for (unsigned i = 0, e = CSI.size(); i != e; ++i) { for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
unsigned Reg = CSI[i].getReg(); unsigned Reg = CSI[i].getReg();
if (Reg == FPReg) if (Reg == FPReg)
// X86RegisterInfo::emitEpilogue will handle restoring of frame register. // X86RegisterInfo::emitEpilogue will handle restoring of frame register.
continue; continue;
if (!X86::VR128RegClass.contains(Reg)) { if (!X86::VR128RegClass.contains(Reg) && !isWin64) {
BuildMI(MBB, MI, DL, get(Opc), Reg); BuildMI(MBB, MI, DL, get(Opc), Reg);
} else { } else {
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(),
&X86::VR128RegClass, &RI); RC, &RI);
} }
} }
return true; return true;