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https://github.com/c64scene-ar/llvm-6502.git
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Correct POP handling for v7m
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225972 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -190,7 +190,7 @@ class ARMAsmParser : public MCTargetAsmParser {
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}
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bool validatetLDMRegList(MCInst Inst, const OperandVector &Operands,
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unsigned ListNo, bool IsPop = false);
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unsigned ListNo, bool IsARPop = false);
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bool validatetSTMRegList(MCInst Inst, const OperandVector &Operands,
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unsigned ListNo);
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@ -6027,7 +6027,7 @@ static bool instIsBreakpoint(const MCInst &Inst) {
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bool ARMAsmParser::validatetLDMRegList(MCInst Inst,
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const OperandVector &Operands,
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unsigned ListNo, bool IsPop) {
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unsigned ListNo, bool IsARPop) {
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const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[ListNo]);
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bool HasWritebackToken = Op.isToken() && Op.getToken() == "!";
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@ -6035,7 +6035,7 @@ bool ARMAsmParser::validatetLDMRegList(MCInst Inst,
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bool ListContainsLR = listContainsReg(Inst, ListNo, ARM::LR);
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bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC);
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if (!IsPop && ListContainsSP)
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if (!IsARPop && ListContainsSP)
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return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
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"SP may not be in the register list");
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else if (ListContainsPC && ListContainsLR)
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@ -6338,7 +6338,7 @@ bool ARMAsmParser::validateInstruction(MCInst &Inst,
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!isThumbTwo())
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return Error(Operands[2]->getStartLoc(),
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"registers must be in range r0-r7 or pc");
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if (validatetLDMRegList(Inst, Operands, 2, /*IsPop=*/true))
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if (validatetLDMRegList(Inst, Operands, 2, !isMClass()))
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return true;
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break;
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}
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@ -1,12 +1,16 @@
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@ RUN: not llvm-mc -triple thumbv7-eabi -filetype asm -o - %s 2>&1 \
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@ RUN: | FileCheck %s
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@ RUN: not llvm-mc -triple thumbv7a-eabi -filetype asm -o - %s 2>&1 \
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@ RUN: | FileCheck --check-prefix=CHECK --check-prefix=CHECK-V7A %s
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@ RUN: not llvm-mc -triple thumbv7m-eabi -filetype asm -o - %s 2>&1 \
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@ RUN: | FileCheck --check-prefix=CHECK --check-prefix=CHECK-V7M %s
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.syntax unified
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.thumb
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.global ldm
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.type ldm,%function
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ldb:
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ldm:
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ldm r0!, {r1, sp}
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@ CHECK: error: SP may not be in the register list
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@ CHECK: ldm r0!, {r1, sp}
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@ -27,7 +31,7 @@ ldb:
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ldmdb:
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ldmdb r0!, {r1, sp}
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@ CHECK: error: SP may not be in the register list
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ldm r0!, {lr, pc}
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ldmdb r0!, {lr, pc}
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@ error: PC and LR may not be in the register list simultaneously
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itt eq
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ldmeq r0!, {r1, pc}
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@ -63,12 +67,14 @@ push:
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@ CHECK: error: SP may not be in the register list
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push {pc}
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@ CHECK: error: PC may not be in the register list
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push {sp,pc}
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push {sp, pc}
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@ CHECK: error: SP and PC may not be in the register list
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.global pop
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.type pop,%function
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pop:
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pop {sp}
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@ CHECK-V7M: error: SP may not be in the register list
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pop {lr, pc}
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@ CHECK: error: PC and LR may not be in the register list simultaneously
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@ CHECK: pop {lr, pc}
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@ -84,9 +90,9 @@ pop:
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.type valid,%function
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valid:
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pop {sp}
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@ CHECK: ldr sp, [sp], #4
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@ CHECK-V7A: ldr sp, [sp], #4
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pop {sp, pc}
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@ CHECK: pop.w {sp, pc}
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@ CHECK-V7A: pop.w {sp, pc}
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push.w {r0}
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@ CHECK: str r0, [sp, #-4]
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pop.w {r0}
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