diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 410cc953e9d..f1b160cdfae 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -7527,7 +7527,8 @@ X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
     // And our return value (tls address) is in the standard call return value
     // location.
     unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
-    return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
+    return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
+                              Chain.getValue(1));
   }
 
   assert(false &&
diff --git a/test/CodeGen/X86/tlv-1.ll b/test/CodeGen/X86/tlv-1.ll
index 5773260f68d..92dac309662 100644
--- a/test/CodeGen/X86/tlv-1.ll
+++ b/test/CodeGen/X86/tlv-1.ll
@@ -5,6 +5,7 @@
 @c = external thread_local global %struct.A, align 4
 
 define void @main() nounwind ssp {
+; CHECK: main:
 entry:
   call void @llvm.memset.p0i8.i64(i8* getelementptr inbounds (%struct.A* @c, i32 0, i32 0, i32 0), i8 0, i64 60, i32 1, i1 false)
   unreachable  
@@ -14,6 +15,22 @@ entry:
   ; CHECK-NEXT: movq    $0, 48(%rax)
 }
 
+; rdar://10291355
+define i32 @test() nounwind readonly ssp {
+entry:
+; CHECK: test:
+; CHECK: movq _a@TLVP(%rip),
+; CHECK: callq *
+; CHECK: movl (%rax), [[REGISTER:%[a-z]+]]
+; CHECK: movq _b@TLVP(%rip),
+; CHECK: callq *
+; CHECK: subl (%rax), [[REGISTER]]
+  %0 = load i32* @a, align 4
+  %1 = load i32* @b, align 4
+  %sub = sub nsw i32 %0, %1
+  ret i32 %sub
+}
+
 declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) nounwind
 
 @a = thread_local global i32 0                    ; <i32*> [#uses=0]