From fd532d7cd925b89daea1a585c0f344a33e81c7fe Mon Sep 17 00:00:00 2001 From: Mon P Wang Date: Fri, 31 Oct 2008 19:13:42 +0000 Subject: [PATCH] x86_64 rip-relative and magic mode address git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58528 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86CodeEmitter.cpp | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/lib/Target/X86/X86CodeEmitter.cpp b/lib/Target/X86/X86CodeEmitter.cpp index 2fe64273b17..12711461401 100644 --- a/lib/Target/X86/X86CodeEmitter.cpp +++ b/lib/Target/X86/X86CodeEmitter.cpp @@ -338,7 +338,7 @@ void Emitter::emitMemModRMByte(const MachineInstr &MI, unsigned BaseReg = Base.getReg(); // Is a SIB byte needed? - if (IndexReg.getReg() == 0 && + if ((!Is64BitMode || DispForReloc) && IndexReg.getReg() == 0 && (BaseReg == 0 || getX86RegNum(BaseReg) != N86::ESP)) { if (BaseReg == 0) { // Just a displacement? // Emit special case [disp32] encoding @@ -395,9 +395,13 @@ void Emitter::emitMemModRMByte(const MachineInstr &MI, if (BaseReg == 0) { // Handle the SIB byte for the case where there is no base. The // displacement has already been output. - assert(IndexReg.getReg() && "Index register must be specified!"); - emitSIBByte(SS, getX86RegNum(IndexReg.getReg()), 5); - } else { + unsigned IndexRegNo; + if (IndexReg.getReg()) + IndexRegNo = getX86RegNum(IndexReg.getReg()); + else + IndexRegNo = 4; // For example [ESP+1*+4] + emitSIBByte(SS, IndexRegNo, 5); + } else { unsigned BaseRegNo = getX86RegNum(BaseReg); unsigned IndexRegNo; if (IndexReg.getReg())