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https://github.com/c64scene-ar/llvm-6502.git
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Mark instructions that are cracked by the PPC970 decoder as such.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26720 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
88d211f823
commit
fd97734f36
@ -72,10 +72,9 @@ def PPCInstrInfo : InstrInfo {
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// should be kept up-to-date with the fields in the PPCInstrInfo.h file.
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let TSFlagsFields = ["PPC970_First",
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"PPC970_Single",
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"PPC970_Cracked",
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"PPC970_Unit"];
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let TSFlagsShifts = [0,
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1,
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2];
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let TSFlagsShifts = [0, 1, 2, 3];
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let isLittleEndianEncoding = 1;
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}
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@ -6,9 +6,6 @@
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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//
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@ -32,11 +29,13 @@ class I<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
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/// these must be reflected there! See comments there for what these are.
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bits<1> PPC970_First = 0;
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bits<1> PPC970_Single = 0;
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bits<1> PPC970_Cracked = 0;
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bits<3> PPC970_Unit = 0;
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}
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class PPC970_DGroup_First { bits<1> PPC970_First = 1; }
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class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; }
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class PPC970_DGroup_First { bits<1> PPC970_First = 1; }
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class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; }
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class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; }
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class PPC970_MicroCode;
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class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; }
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@ -37,9 +37,13 @@ enum {
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/// terminates it, so it will be the sole instruction in the group.
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PPC970_Single = 0x2,
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/// PPC970_Cracked - This instruction is cracked into two pieces, requiring
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/// two dispatch pipes to be available to issue.
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PPC970_Cracked = 0x4,
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/// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that
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/// an instruction is issued to.
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PPC970_Shift = 2,
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PPC970_Shift = 3,
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PPC970_Mask = 0x07 << PPC970_Shift,
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};
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enum PPC970_Unit {
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@ -293,7 +293,8 @@ def LBZ : DForm_1<34, (ops GPRC:$rD, memri:$src),
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[(set GPRC:$rD, (zextload iaddr:$src, i8))]>;
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def LHA : DForm_1<42, (ops GPRC:$rD, memri:$src),
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"lha $rD, $src", LdStLHA,
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[(set GPRC:$rD, (sextload iaddr:$src, i16))]>;
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[(set GPRC:$rD, (sextload iaddr:$src, i16))]>,
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PPC970_DGroup_Cracked;
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def LHZ : DForm_1<40, (ops GPRC:$rD, memri:$src),
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"lhz $rD, $src", LdStGeneral,
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[(set GPRC:$rD, (zextload iaddr:$src, i16))]>;
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@ -313,7 +314,8 @@ def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
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[(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
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def ADDIC : DForm_2<12, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
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"addic $rD, $rA, $imm", IntGeneral,
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[(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))]>;
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[(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))]>,
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PPC970_DGroup_Cracked;
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def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
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"addic. $rD, $rA, $imm", IntGeneral,
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[]>;
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@ -412,7 +414,7 @@ def STFD : DForm_9<54, (ops F8RC:$rS, memri:$dst),
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let isLoad = 1, PPC970_Unit = 2 in {
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def LWA : DSForm_1<58, 2, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
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"lwa $rT, $DS($rA)", LdStLWA,
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[]>, isPPC64;
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[]>, isPPC64, PPC970_DGroup_Cracked;
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def LD : DSForm_2<58, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
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"ld $rT, $DS($rA)", LdStLD,
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[]>, isPPC64;
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@ -435,13 +437,15 @@ def LBZX : XForm_1<31, 87, (ops GPRC:$rD, memrr:$src),
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[(set GPRC:$rD, (zextload xaddr:$src, i8))]>;
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def LHAX : XForm_1<31, 343, (ops GPRC:$rD, memrr:$src),
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"lhax $rD, $src", LdStLHA,
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[(set GPRC:$rD, (sextload xaddr:$src, i16))]>;
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[(set GPRC:$rD, (sextload xaddr:$src, i16))]>,
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PPC970_DGroup_Cracked;
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def LHZX : XForm_1<31, 279, (ops GPRC:$rD, memrr:$src),
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"lhzx $rD, $src", LdStGeneral,
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[(set GPRC:$rD, (zextload xaddr:$src, i16))]>;
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def LWAX : XForm_1<31, 341, (ops G8RC:$rD, memrr:$src),
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"lwax $rD, $src", LdStLHA,
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[(set G8RC:$rD, (sextload xaddr:$src, i32))]>, isPPC64;
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[(set G8RC:$rD, (sextload xaddr:$src, i32))]>, isPPC64,
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PPC970_DGroup_Cracked;
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def LWZX : XForm_1<31, 23, (ops GPRC:$rD, memrr:$src),
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"lwzx $rD, $src", LdStGeneral,
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[(set GPRC:$rD, (load xaddr:$src))]>;
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@ -529,19 +533,22 @@ def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
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def STBX : XForm_8<31, 215, (ops GPRC:$rS, memrr:$dst),
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"stbx $rS, $dst", LdStGeneral,
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[(truncstore GPRC:$rS, xaddr:$dst, i8)]>;
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[(truncstore GPRC:$rS, xaddr:$dst, i8)]>,
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PPC970_DGroup_Cracked;
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def STHX : XForm_8<31, 407, (ops GPRC:$rS, memrr:$dst),
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"sthx $rS, $dst", LdStGeneral,
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[(truncstore GPRC:$rS, xaddr:$dst, i16)]>;
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[(truncstore GPRC:$rS, xaddr:$dst, i16)]>,
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PPC970_DGroup_Cracked;
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def STWX : XForm_8<31, 151, (ops GPRC:$rS, memrr:$dst),
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"stwx $rS, $dst", LdStGeneral,
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[(store GPRC:$rS, xaddr:$dst)]>;
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[(store GPRC:$rS, xaddr:$dst)]>,
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PPC970_DGroup_Cracked;
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def STWUX : XForm_8<31, 183, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
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"stwux $rS, $rA, $rB", LdStGeneral,
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[]>;
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def STDX : XForm_8<31, 149, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
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"stdx $rS, $rA, $rB", LdStSTD,
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[]>, isPPC64;
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[]>, isPPC64, PPC970_DGroup_Cracked;
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def STDUX : XForm_8<31, 181, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
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"stdux $rS, $rA, $rB", LdStSTD,
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[]>, isPPC64;
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@ -721,26 +728,27 @@ def ADD8 : XOForm_1<31, 266, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
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[(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>;
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def ADDC : XOForm_1<31, 10, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
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"addc $rT, $rA, $rB", IntGeneral,
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[(set GPRC:$rT, (addc GPRC:$rA, GPRC:$rB))]>;
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[(set GPRC:$rT, (addc GPRC:$rA, GPRC:$rB))]>,
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PPC970_DGroup_Cracked;
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def ADDE : XOForm_1<31, 138, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
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"adde $rT, $rA, $rB", IntGeneral,
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[(set GPRC:$rT, (adde GPRC:$rA, GPRC:$rB))]>;
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def DIVD : XOForm_1<31, 489, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
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"divd $rT, $rA, $rB", IntDivD,
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[(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64,
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PPC970_DGroup_First;
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PPC970_DGroup_First, PPC970_DGroup_Cracked;
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def DIVDU : XOForm_1<31, 457, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
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"divdu $rT, $rA, $rB", IntDivD,
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[(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64,
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PPC970_DGroup_First;
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PPC970_DGroup_First, PPC970_DGroup_Cracked;
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def DIVW : XOForm_1<31, 491, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
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"divw $rT, $rA, $rB", IntDivW,
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[(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>,
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PPC970_DGroup_First;
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PPC970_DGroup_First, PPC970_DGroup_Cracked;
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def DIVWU : XOForm_1<31, 459, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
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"divwu $rT, $rA, $rB", IntDivW,
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[(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>,
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PPC970_DGroup_First;
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PPC970_DGroup_First, PPC970_DGroup_Cracked;
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def MULHD : XOForm_1<31, 73, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
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"mulhd $rT, $rA, $rB", IntMulHW,
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[(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>;
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@ -764,7 +772,8 @@ def SUBF : XOForm_1<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
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[(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
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def SUBFC : XOForm_1<31, 8, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
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"subfc $rT, $rA, $rB", IntGeneral,
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[(set GPRC:$rT, (subc GPRC:$rB, GPRC:$rA))]>;
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[(set GPRC:$rT, (subc GPRC:$rB, GPRC:$rA))]>,
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PPC970_DGroup_Cracked;
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def SUBFE : XOForm_1<31, 136, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
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"subfe $rT, $rA, $rB", IntGeneral,
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[(set GPRC:$rT, (sube GPRC:$rB, GPRC:$rA))]>;
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@ -891,7 +900,7 @@ let isTwoAddress = 1, isCommutable = 1 in {
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def RLWIMI : MForm_2<20,
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(ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
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u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
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[]>;
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[]>, PPC970_DGroup_Cracked;
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def RLDIMI : MDForm_1<30, 3,
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(ops G8RC:$rA, G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB),
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"rldimi $rA, $rS, $SH, $MB", IntRotateD,
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@ -904,7 +913,7 @@ def RLWINM : MForm_2<21,
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def RLWINMo : MForm_2<21,
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(ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
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"rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
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[]>, isDOT;
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[]>, isDOT, PPC970_DGroup_Cracked;
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def RLWNM : MForm_2<23,
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(ops GPRC:$rA, GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
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"rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral,
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