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[mips] Change type of accumulator registers to Untyped. Add two more accumulator
register classes for Mips64 and DSP-ASE. No functionality changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178328 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -58,6 +58,13 @@ class AFPR64<bits<16> Enc, string n, list<Register> subregs>
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let SubRegIndices = [sub_32];
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}
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// Accumulator Registers
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class ACC<bits<16> Enc, string n, list<Register> subregs>
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: MipsRegWithSubRegs<Enc, n, subregs> {
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let SubRegIndices = [sub_lo, sub_hi];
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let CoveredBySubRegs = 1;
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}
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// Mips Hardware Registers
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class HWR<bits<16> Enc, string n> : MipsReg<Enc, n>;
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@ -223,7 +230,13 @@ let Namespace = "Mips" in {
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// Hi/Lo registers
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def HI : Register<"hi">, DwarfRegNum<[64]>;
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def HI1 : Register<"hi1">, DwarfRegNum<[176]>;
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def HI2 : Register<"hi2">, DwarfRegNum<[178]>;
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def HI3 : Register<"hi3">, DwarfRegNum<[180]>;
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def LO : Register<"lo">, DwarfRegNum<[65]>;
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def LO1 : Register<"lo1">, DwarfRegNum<[177]>;
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def LO2 : Register<"lo2">, DwarfRegNum<[179]>;
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def LO3 : Register<"lo3">, DwarfRegNum<[181]>;
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let SubRegIndices = [sub_32] in {
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def HI64 : RegisterWithSubRegs<"hi", [HI]>;
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@ -244,11 +257,12 @@ let Namespace = "Mips" in {
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def HWR29_64 : MipsReg<29, "29">;
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// Accum registers
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let SubRegIndices = [sub_lo, sub_hi] in
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def AC0 : MipsRegWithSubRegs<0, "ac0", [LO, HI]>;
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def AC1 : MipsReg<1, "ac1">;
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def AC2 : MipsReg<2, "ac2">;
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def AC3 : MipsReg<3, "ac3">;
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def AC0 : ACC<0, "ac0", [LO, HI]>;
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def AC1 : ACC<1, "ac1", [LO1, HI1]>;
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def AC2 : ACC<2, "ac2", [LO2, HI2]>;
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def AC3 : ACC<3, "ac3", [LO3, HI3]>;
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def AC0_64 : ACC<0, "ac0", [LO64, HI64]>;
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def DSPCtrl : Register<"dspctrl">;
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}
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@ -334,8 +348,17 @@ def HWRegs : RegisterClass<"Mips", [i32], 32, (add HWR29)>, Unallocatable;
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def HWRegs64 : RegisterClass<"Mips", [i64], 64, (add HWR29_64)>, Unallocatable;
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// Accumulator Registers
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def ACRegs : RegisterClass<"Mips", [i64], 64, (sequence "AC%u", 0, 3)>,
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Unallocatable;
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def ACRegs : RegisterClass<"Mips", [untyped], 64, (add AC0)> {
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let Size = 64;
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}
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def ACRegs128 : RegisterClass<"Mips", [untyped], 128, (add AC0_64)> {
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let Size = 128;
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}
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def ACRegsDSP : RegisterClass<"Mips", [untyped], 64, (sequence "AC%u", 0, 3)> {
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let Size = 64;
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}
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def CPURegsAsmOperand : AsmOperandClass {
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let Name = "CPURegsAsm";
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