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X86: Don't transform shifts into ands when the sign bit is tested.

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Should unbreak MultiSource/Benchmarks/mediabench/g721/g721encode/encode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207145 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Benjamin Kramer 2014-04-24 20:51:37 +00:00
parent 1ce40b302d
commit fda5e19b96
2 changed files with 13 additions and 1 deletions
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3
lib/Target/X86/X86ISelLowering.cpp
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@ -9802,7 +9802,8 @@ SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
// If we have a constant logical shift that's only used in a comparison
// against zero turn it into an equivalent AND. This allows turning it into
// a TEST instruction later.
if (isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) &&
isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
EVT VT = Op.getValueType();
unsigned BitWidth = VT.getSizeInBits();
unsigned ShAmt = Op->getConstantOperandVal(1);

11
test/CodeGen/X86/cmp.ll
View File

@ -187,3 +187,14 @@ define i32 @test13(i32 %mask, i32 %base, i32 %intra) {
; CHECK: testb $8, %dil
; CHECK: cmovnel
}
define i32 @test14(i32 %mask, i32 %base, i32 %intra) #0 {
%s = lshr i32 %mask, 7
%tobool = icmp sgt i32 %s, -1
%cond = select i1 %tobool, i32 %intra, i32 %base
ret i32 %cond
; CHECK-LABEL: test14:
; CHECK: shrl $7, %edi
; CHECK-NEXT: cmovnsl %edx, %esi
}