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reduce nesting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99358 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -473,7 +473,7 @@ def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
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def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
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return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
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else {
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unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
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APInt Mask = APInt::getAllOnesValue(BitWidth);
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APInt KnownZero0, KnownOne0;
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@ -481,7 +481,6 @@ def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
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APInt KnownZero1, KnownOne1;
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CurDAG->ComputeMaskedBits(N->getOperand(1), Mask, KnownZero1, KnownOne1, 0);
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return (~KnownZero0 & ~KnownZero1) == 0;
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}
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}]>;
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// 'shld' and 'shrd' instruction patterns. Note that even though these have
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