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Fix BXJ is undefined in AArch32.
BXJ was incorrectly said to be unsupported in ARMv8-A. It is not supported in the A64 instruction set, but it is supported in the T32 and A32 instruction sets, because it's listed as an instruction in the ARM ARM section F7.1.28. Using SP as an operand to BXJ changed from UNPREDICTABLE to PREDICTABLE in v8-A. This patch reflects that update as well. This was found by MCHammer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235024 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -3630,8 +3630,8 @@ def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
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// Branch and Exchange Jazelle -- for disassembly only
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// Rm = Inst{19-16}
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def t2BXJ : T2I<(outs), (ins rGPR:$func), NoItinerary, "bxj", "\t$func", []>,
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Sched<[WriteBr]>, Requires<[IsThumb2, IsNotMClass, PreV8]> {
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def t2BXJ : T2I<(outs), (ins GPRnopc:$func), NoItinerary, "bxj", "\t$func", []>,
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Sched<[WriteBr]>, Requires<[IsThumb2, IsNotMClass]> {
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bits<4> func;
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let Inst{31-27} = 0b11110;
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let Inst{26} = 0;
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@ -6150,6 +6150,14 @@ bool ARMAsmParser::validateInstruction(MCInst &Inst,
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"destination operands can't be identical");
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return false;
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}
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case ARM::t2BXJ: {
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const unsigned RmReg = Inst.getOperand(0).getReg();
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// Rm = SP is no longer unpredictable in v8-A
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if (RmReg == ARM::SP && !hasV8Ops())
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return Error(Operands[2]->getStartLoc(),
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"r13 (SP) is an unpredictable operand to BXJ");
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return false;
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}
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case ARM::STRD: {
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// Rt2 must be Rt + 1.
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unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
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11
test/MC/ARM/thumb2-bxj-v8.s
Normal file
11
test/MC/ARM/thumb2-bxj-v8.s
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@ -0,0 +1,11 @@
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@ RUN: not llvm-mc -triple=thumbv6t2--none-eabi -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=UNDEF
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@ RUN: not llvm-mc -triple=thumbv7a--none-eabi -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=UNDEF
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@ RUN: not llvm-mc -triple=thumbv7r--none-eabi -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=UNDEF
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@ RUN: not llvm-mc -triple=thumbv7m--none-eabi -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=ARM_MODE
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@ RUN: llvm-mc -triple=thumbv8a--none-eabi -show-encoding < %s 2>&1 | FileCheck %s
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bxj r13
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@ CHECK: bxj sp @ encoding: [0xcd,0xf3,0x00,0x8f]
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@ UNDEF: error: r13 (SP) is an unpredictable operand to BXJ
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@ ARM_MODE: error: instruction requires: arm-mode
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@ -1,8 +1,8 @@
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@ RUN: llvm-mc -triple=thumbv6t2--none-eabi -show-encoding < %s | FileCheck %s
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@ RUN: llvm-mc -triple=thumbv7a--none-eabi -show-encoding < %s | FileCheck %s
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@ RUN: llvm-mc -triple=thumbv7r--none-eabi -show-encoding < %s | FileCheck %s
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@ RUN: llvm-mc -triple=thumbv8a--none-eabi -show-encoding < %s | FileCheck %s
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@ RUN: not llvm-mc -triple=thumbv7m--none-eabi -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=UNDEF
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@ RUN: not llvm-mc -triple=thumbv8a--none-eabi -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=UNDEF
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bxj r2
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