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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64827 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Scott Michel 2009-02-17 22:15:04 +00:00
parent 36375ee7a5
commit fdc40a0a69
10 changed files with 1729 additions and 1729 deletions
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64
include/llvm/CodeGen/SelectionDAG.h
View File

@ -143,7 +143,7 @@ public:
///
void viewGraph(const std::string &Title);
void viewGraph();
#ifndef NDEBUG
std::map<const SDNode *, std::string> NodeGraphAttrs;
#endif
@ -151,15 +151,15 @@ public:
/// clearGraphAttrs - Clear all previously defined node graph attributes.
/// Intended to be used from a debugging tool (eg. gdb).
void clearGraphAttrs();
/// setGraphAttrs - Set graph attributes for a node. (eg. "color=red".)
///
void setGraphAttrs(const SDNode *N, const char *Attrs);
/// getGraphAttrs - Get graph attributes for a node. (eg. "color=red".)
/// Used from getNodeAttributes.
const std::string getGraphAttrs(const SDNode *N) const;
/// setGraphColor - Convenience for setting node color attribute.
///
void setGraphColor(const SDNode *N, const char *Color);
@ -177,7 +177,7 @@ public:
ilist<SDNode>::size_type allnodes_size() const {
return AllNodes.size();
}
/// getRoot - Return the root tag of the SelectionDAG.
///
const SDValue &getRoot() const { return Root; }
@ -233,7 +233,7 @@ public:
SDVTList getVTList(MVT VT1, MVT VT2, MVT VT3);
SDVTList getVTList(MVT VT1, MVT VT2, MVT VT3, MVT VT4);
SDVTList getVTList(const MVT *VTs, unsigned NumVTs);
/// getNodeValueTypes - These are obsolete, use getVTList instead.
const MVT *getNodeValueTypes(MVT VT) {
return getVTList(VT).VTs;
@ -250,8 +250,8 @@ public:
const MVT *getNodeValueTypes(const std::vector<MVT> &vtList) {
return getVTList(&vtList[0], (unsigned)vtList.size()).VTs;
}
//===--------------------------------------------------------------------===//
// Node creation methods.
//
@ -320,7 +320,7 @@ public:
SDValue getRegister(unsigned Reg, MVT VT);
SDValue getDbgStopPoint(SDValue Root, unsigned Line, unsigned Col,
Value *CU);
SDValue getLabel(unsigned Opcode, DebugLoc dl, SDValue Root,
SDValue getLabel(unsigned Opcode, DebugLoc dl, SDValue Root,
unsigned LabelID);
SDValue getCopyToReg(SDValue Chain, DebugLoc dl, unsigned Reg, SDValue N) {
@ -345,13 +345,13 @@ public:
SDValue Ops[] = { Chain, Reg, N, Flag };
return getNode(ISD::CopyToReg, dl, VTs, 2, Ops, Flag.getNode() ? 4 : 3);
}
SDValue getCopyFromReg(SDValue Chain, DebugLoc dl, unsigned Reg, MVT VT) {
const MVT *VTs = getNodeValueTypes(VT, MVT::Other);
SDValue Ops[] = { Chain, getRegister(Reg, VT) };
return getNode(ISD::CopyFromReg, dl, VTs, 2, Ops, 2);
}
// This version of the getCopyFromReg method takes an extra operand, which
// indicates that there is potentially an incoming flag value (if Flag is not
// null) and that there should be a flag result.
@ -373,7 +373,7 @@ public:
/// getZeroExtendInReg - Return the expression required to zero extend the Op
/// value assuming it was the smaller SrcTy value.
SDValue getZeroExtendInReg(SDValue Op, DebugLoc DL, MVT SrcTy);
/// getNOT - Create a bitwise NOT operation as (XOR Val, -1).
SDValue getNOT(DebugLoc DL, SDValue Val, MVT VT);
@ -383,7 +383,7 @@ public:
SDValue getCALLSEQ_START(SDValue Chain, SDValue Op) {
const MVT *VTs = getNodeValueTypes(MVT::Other, MVT::Flag);
SDValue Ops[] = { Chain, Op };
return getNode(ISD::CALLSEQ_START, DebugLoc::getUnknownLoc(),
return getNode(ISD::CALLSEQ_START, DebugLoc::getUnknownLoc(),
VTs, 2, Ops, 2);
}
@ -399,7 +399,7 @@ public:
Ops.push_back(Op2);
Ops.push_back(InFlag);
return getNode(ISD::CALLSEQ_END, DebugLoc::getUnknownLoc(), NodeTys,
&Ops[0],
&Ops[0],
(unsigned)Ops.size() - (InFlag.getNode() == 0 ? 1 : 0));
}
@ -487,15 +487,15 @@ public:
return getNode(ISD::SELECT_CC, DL, True.getValueType(),
LHS, RHS, True, False, getCondCode(Cond));
}
/// getVAArg - VAArg produces a result and token chain, and takes a pointer
/// and a source value as input.
SDValue getVAArg(MVT VT, DebugLoc dl, SDValue Chain, SDValue Ptr,
SDValue SV);
/// getAtomic - Gets a node for an atomic op, produces result and chain and
/// getAtomic - Gets a node for an atomic op, produces result and chain and
/// takes 3 operands
SDValue getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT, SDValue Chain,
SDValue getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT, SDValue Chain,
SDValue Ptr, SDValue Cmp, SDValue Swp, const Value* PtrVal,
unsigned Alignment=0);
@ -585,7 +585,7 @@ public:
SDValue Op3, SDValue Op4, SDValue Op5);
SDValue UpdateNodeOperands(SDValue N,
const SDValue *Ops, unsigned NumOps);
/// SelectNodeTo - These are used for target selectors to *mutate* the
/// specified node to have the specified return type, Target opcode, and
/// operands. Note that target opcodes are stored as
@ -649,14 +649,14 @@ public:
/// the current one.
SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT);
SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, SDValue Op1);
SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, SDValue Op1,
SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, SDValue Op1,
SDValue Op2);
SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
SDValue Op1, SDValue Op2, SDValue Op3);
SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
const SDValue *Ops, unsigned NumOps);
SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2);
SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2,
SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2,
SDValue Op1);
SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
MVT VT2, SDValue Op1, SDValue Op2);
@ -680,7 +680,7 @@ public:
/// else return NULL.
SDNode *getNodeIfExists(unsigned Opcode, SDVTList VTs,
const SDValue *Ops, unsigned NumOps);
/// DAGUpdateListener - Clients of various APIs that cause global effects on
/// the DAG can optionally implement this interface. This allows the clients
/// to handle the various sorts of updates that happen.
@ -695,12 +695,12 @@ public:
/// NodeUpdated - The node N that was updated.
virtual void NodeUpdated(SDNode *N) = 0;
};
/// RemoveDeadNode - Remove the specified node from the system. If any of its
/// operands then becomes dead, remove them as well. Inform UpdateListener
/// for each node deleted.
void RemoveDeadNode(SDNode *N, DAGUpdateListener *UpdateListener = 0);
/// RemoveDeadNodes - This method deletes the unreachable nodes in the
/// given list, and any nodes that become unreachable as a result.
void RemoveDeadNodes(SmallVectorImpl<SDNode *> &DeadNodes,
@ -711,7 +711,7 @@ public:
/// version if 'From' is known to have a single result, use the second
/// if you have two nodes with identical results, use the third otherwise.
///
/// These methods all take an optional UpdateListener, which (if not null) is
/// These methods all take an optional UpdateListener, which (if not null) is
/// informed about nodes that are deleted and modified due to recursive
/// changes in the dag.
///
@ -768,7 +768,7 @@ public:
case ISD::AND:
case ISD::OR:
case ISD::XOR:
case ISD::ADDC:
case ISD::ADDC:
case ISD::ADDE: return true;
default: return false;
}
@ -785,7 +785,7 @@ public:
/// either of the specified value types.
SDValue CreateStackTemporary(MVT VT1, MVT VT2);
/// FoldConstantArithmetic -
/// FoldConstantArithmetic -
SDValue FoldConstantArithmetic(unsigned Opcode,
MVT VT,
ConstantSDNode *Cst1,
@ -794,7 +794,7 @@ public:
/// FoldSetCC - Constant fold a setcc to true or false.
SDValue FoldSetCC(MVT VT, SDValue N1,
SDValue N2, ISD::CondCode Cond, DebugLoc dl);
/// SignBitIsZero - Return true if the sign bit of Op is known to be zero. We
/// use this predicate to simplify operations downstream.
bool SignBitIsZero(SDValue Op, unsigned Depth = 0) const;
@ -804,11 +804,11 @@ public:
/// known to be the same type.
bool MaskedValueIsZero(SDValue Op, const APInt &Mask, unsigned Depth = 0)
const;
/// ComputeMaskedBits - Determine which of the bits specified in Mask are
/// known to be either zero or one and return them in the KnownZero/KnownOne
/// bitsets. This code only analyzes bits in Mask, in order to short-circuit
/// processing. Targets can implement the computeMaskedBitsForTargetNode
/// processing. Targets can implement the computeMaskedBitsForTargetNode
/// method in the TargetLowering class to allow target nodes to be understood.
void ComputeMaskedBits(SDValue Op, const APInt &Mask, APInt &KnownZero,
APInt &KnownOne, unsigned Depth = 0) const;
@ -829,7 +829,7 @@ public:
/// getShuffleScalarElt - Returns the scalar element that will make up the ith
/// element of the result of the vector shuffle.
SDValue getShuffleScalarElt(const SDNode *N, unsigned Idx);
private:
bool RemoveNodeFromCSEMaps(SDNode *N);
void AddModifiedNodeToCSEMaps(SDNode *N, DAGUpdateListener *UpdateListener);
@ -845,10 +845,10 @@ private:
unsigned getMVTAlignment(MVT MemoryVT) const;
void allnodes_clear();
/// VTList - List of non-single value types.
std::vector<SDVTList> VTList;
/// CondCodeNodes - Maps to auto-CSE operations.
std::vector<CondCodeSDNode*> CondCodeNodes;

176
include/llvm/CodeGen/SelectionDAGNodes.h
View File

@ -78,7 +78,7 @@ namespace ISD {
// DELETED_NODE - This is an illegal flag value that is used to catch
// errors. This opcode is not a legal opcode for any node.
DELETED_NODE,
// EntryToken - This is the marker used to indicate the start of the region.
EntryToken,
@ -86,10 +86,10 @@ namespace ISD {
// single token result. This is used to represent the fact that the operand
// operators are independent of each other.
TokenFactor,
// AssertSext, AssertZext - These nodes record if a register contains a
// value that has already been zero or sign extended from a narrower type.
// These nodes take two operands. The first is the node that has already
// AssertSext, AssertZext - These nodes record if a register contains a
// value that has already been zero or sign extended from a narrower type.
// These nodes take two operands. The first is the node that has already
// been extended, and the second is a value type node indicating the width
// of the extension
AssertSext, AssertZext,
@ -102,7 +102,7 @@ namespace ISD {
// The address of the GOT
GLOBAL_OFFSET_TABLE,
// FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and
// llvm.returnaddress on the DAG. These nodes take one operand, the index
// of the frame or return address to return. An index of zero corresponds
@ -114,11 +114,11 @@ namespace ISD {
// first (possible) on-stack argument. This is needed for correct stack
// adjustment during unwind.
FRAME_TO_ARGS_OFFSET,
// RESULT, OUTCHAIN = EXCEPTIONADDR(INCHAIN) - This node represents the
// address of the exception block on entry to an landing pad block.
EXCEPTIONADDR,
// RESULT, OUTCHAIN = EHSELECTION(INCHAIN, EXCEPTION) - This node represents
// the selection index of the exception thrown.
EHSELECTION,
@ -133,7 +133,7 @@ namespace ISD {
// simplification of the constant.
TargetConstant,
TargetConstantFP,
// TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or
// anything else with this node, and this is valid in the target-specific
// dag, turning into a GlobalAddress operand.
@ -143,14 +143,14 @@ namespace ISD {
TargetJumpTable,
TargetConstantPool,
TargetExternalSymbol,
/// RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...)
/// This node represents a target intrinsic function with no side effects.
/// The first operand is the ID number of the intrinsic from the
/// llvm::Intrinsic namespace. The operands to the intrinsic follow. The
/// node has returns the result of the intrinsic.
INTRINSIC_WO_CHAIN,
/// RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...)
/// This node represents a target intrinsic function with side effects that
/// returns a result. The first operand is a chain pointer. The second is
@ -165,9 +165,9 @@ namespace ISD {
/// second is the ID number of the intrinsic from the llvm::Intrinsic
/// namespace. The operands to the intrinsic follow.
INTRINSIC_VOID,
// CopyToReg - This node has three operands: a chain, a register number to
// set to this value, and a value.
// set to this value, and a value.
CopyToReg,
// CopyFromReg - This node indicates that the input value is a virtual or
@ -177,7 +177,7 @@ namespace ISD {
// UNDEF - An undefined node
UNDEF,
/// FORMAL_ARGUMENTS(CHAIN, CC#, ISVARARG, FLAG0, ..., FLAGn) - This node
/// represents the formal arguments for a function. CC# is a Constant value
/// indicating the calling convention of the function, and ISVARARG is a
@ -185,9 +185,9 @@ namespace ISD {
/// has one result value for each incoming argument, plus one for the output
/// chain. It must be custom legalized. See description of CALL node for
/// FLAG argument contents explanation.
///
///
FORMAL_ARGUMENTS,
/// RV1, RV2...RVn, CHAIN = CALL(CHAIN, CALLEE,
/// ARG0, FLAG0, ARG1, FLAG1, ... ARGn, FLAGn)
/// This node represents a fully general function call, before the legalizer
@ -239,17 +239,17 @@ namespace ISD {
// SDIVREM/UDIVREM - Divide two integers and produce both a quotient and
// remainder result.
SDIVREM, UDIVREM,
// CARRY_FALSE - This node is used when folding other nodes,
// like ADDC/SUBC, which indicate the carry result is always false.
CARRY_FALSE,
// Carry-setting nodes for multiple precision addition and subtraction.
// These nodes take two operands of the same value type, and produce two
// results. The first result is the normal add or sub result, the second
// result is the carry flag result.
ADDC, SUBC,
// Carry-using nodes for multiple precision addition and subtraction. These
// nodes take three operands: The first two are the normal lhs and rhs to
// the add or sub, and the third is the input carry flag. These nodes
@ -286,12 +286,12 @@ namespace ISD {
// INT = FGETSIGN(FP) - Return the sign bit of the specified floating point
// value as an integer 0/1 value.
FGETSIGN,
/// BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector
/// with the specified, possibly variable, elements. The number of elements
/// is required to be a power of two.
BUILD_VECTOR,
/// INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element
/// at IDX replaced with VAL. If the type of VAL is larger than the vector
/// element type then VAL is truncated before replacement.
@ -300,13 +300,13 @@ namespace ISD {
/// EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR
/// identified by the (potentially variable) element number IDX.
EXTRACT_VECTOR_ELT,
/// CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of
/// vector type with the same length and element type, this produces a
/// concatenated vector result value, with length equal to the sum of the
/// lengths of the input vectors.
CONCAT_VECTORS,
/// EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR (an
/// vector value) starting with the (potentially variable) element number
/// IDX, which must be a multiple of the result vector length.
@ -325,19 +325,19 @@ namespace ISD {
/// scalar value into element 0 of the resultant vector type. The top
/// elements 1 to N-1 of the N-element vector are undefined.
SCALAR_TO_VECTOR,
// EXTRACT_SUBREG - This node is used to extract a sub-register value.
// EXTRACT_SUBREG - This node is used to extract a sub-register value.
// This node takes a superreg and a constant sub-register index as operands.
// Note sub-register indices must be increasing. That is, if the
// sub-register index of a 8-bit sub-register is N, then the index for a
// 16-bit sub-register must be at least N+1.
EXTRACT_SUBREG,
// INSERT_SUBREG - This node is used to insert a sub-register value.
// INSERT_SUBREG - This node is used to insert a sub-register value.
// This node takes a superreg, a subreg value, and a constant sub-register
// index as operands.
INSERT_SUBREG,
// MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing
// an unsigned/signed value of type i[2*N], then return the top part.
MULHU, MULHS,
@ -354,9 +354,9 @@ namespace ISD {
// i1 then the high bits must conform to getBooleanContents.
SELECT,
// Select with condition operator - This selects between a true value and
// Select with condition operator - This selects between a true value and
// a false value (ops #2 and #3) based on the boolean result of comparing
// the lhs and rhs (ops #0 and #1) of a conditional expression with the
// the lhs and rhs (ops #0 and #1) of a conditional expression with the
// condition code in op #4, a CondCodeSDNode.
SELECT_CC,
@ -369,7 +369,7 @@ namespace ISD {
// Vector SetCC operator - This evaluates to a vector of integer elements
// with the high bit in each element set to true if the comparison is true
// and false if the comparison is false. All other bits in each element
// and false if the comparison is false. All other bits in each element
// are undefined. The operands to this are the left and right operands
// to compare (ops #0, and #1) and the condition code to compare them with
// (op #2) as a CondCodeSDNode.
@ -395,7 +395,7 @@ namespace ISD {
// ANY_EXTEND - Used for integer types. The high bits are undefined.
ANY_EXTEND,
// TRUNCATE - Completely drop the high bits.
TRUNCATE,
@ -425,10 +425,10 @@ namespace ISD {
/// The TRUNC = 1 case is used in cases where we know that the value will
/// not be modified by the node, because Y is not using any of the extra
/// precision of source type. This allows certain transformations like
/// FP_EXTEND(FP_ROUND(X,1)) -> X which are not safe for
/// FP_EXTEND(FP_ROUND(X,1)) -> X which are not safe for
/// FP_EXTEND(FP_ROUND(X,0)) because the extra bits aren't removed.
FP_ROUND,
// FLT_ROUNDS_ - Returns current rounding mode:
// -1 Undefined
// 0 Round to 0
@ -449,12 +449,12 @@ namespace ISD {
// BIT_CONVERT - Theis operator converts between integer and FP values, as
// if one was stored to memory as integer and the other was loaded from the
// same address (or equivalently for vector format conversions, etc). The
// source and result are required to have the same bit size (e.g.
// f32 <-> i32). This can also be used for int-to-int or fp-to-fp
// same address (or equivalently for vector format conversions, etc). The
// source and result are required to have the same bit size (e.g.
// f32 <-> i32). This can also be used for int-to-int or fp-to-fp
// conversions, but that is a noop, deleted by getNode().
BIT_CONVERT,
// CONVERT_RNDSAT - This operator is used to support various conversions
// between various types (float, signed, unsigned and vectors of those
// types) with rounding and saturation. NOTE: Avoid using this operator as
@ -467,7 +467,7 @@ namespace ISD {
// 4) saturation imm
// 5) ISD::CvtCode indicating the type of conversion to do
CONVERT_RNDSAT,
// FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW,
// FLOG, FLOG2, FLOG10, FEXP, FEXP2,
// FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR - Perform various unary floating
@ -475,7 +475,7 @@ namespace ISD {
FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW,
FLOG, FLOG2, FLOG10, FEXP, FEXP2,
FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR,
// LOAD and STORE have token chains as their first operand, then the same
// operands as an LLVM load/store instruction, then an offset node that
// is added / subtracted from the base pointer to form the address (for
@ -517,7 +517,7 @@ namespace ISD {
// compare, rather than as a combined SetCC node. The operands in order are
// chain, cc, lhs, rhs, block to branch to if condition is true.
BR_CC,
// RET - Return from function. The first operand is the chain,
// and any subsequent operands are pairs of return value and return value
// attributes (see CALL for description of attributes) for the function.
@ -532,7 +532,7 @@ namespace ISD {
// Operand #2n+3: A TargetConstant, indicating if the reg is a use/def
// Operand #last: Optional, an incoming flag.
INLINEASM,
// DBG_LABEL, EH_LABEL - Represents a label in mid basic block used to track
// locations needed for debug and exception handling tables. These nodes
// take a chain as input and return a chain.
@ -544,16 +544,16 @@ namespace ISD {
// a chain, while the next two operands are first two arguments (address
// and variable) of a llvm.dbg.declare instruction.
DECLARE,
// STACKSAVE - STACKSAVE has one operand, an input chain. It produces a
// value, the same type as the pointer type for the system, and an output
// chain.
STACKSAVE,
// STACKRESTORE has two operands, an input chain and a pointer to restore to
// it returns an output chain.
STACKRESTORE,
// CALLSEQ_START/CALLSEQ_END - These operators mark the beginning and end of
// a call sequence, and carry arbitrary information that target might want
// to know. The first operand is a chain, the rest are specified by the
@ -561,16 +561,16 @@ namespace ISD {
// CALLSEQ_START..CALLSEQ_END pairs may not be nested.
CALLSEQ_START, // Beginning of a call sequence
CALLSEQ_END, // End of a call sequence
// VAARG - VAARG has three operands: an input chain, a pointer, and a
// VAARG - VAARG has three operands: an input chain, a pointer, and a
// SRCVALUE. It returns a pair of values: the vaarg value and a new chain.
VAARG,
// VACOPY - VACOPY has five operands: an input chain, a destination pointer,
// a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the
// source.
VACOPY,
// VAEND, VASTART - VAEND and VASTART have three operands: an input chain, a
// pointer, and a SRCVALUE.
VAEND, VASTART,
@ -589,7 +589,7 @@ namespace ISD {
// READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
// The only operand is a chain and a value and a chain are produced. The
// value is the contents of the architecture specific cycle counter like
// value is the contents of the architecture specific cycle counter like
// register (or other high accuracy low latency clock source)
READCYCLECOUNTER,
@ -601,7 +601,7 @@ namespace ISD {
// column number, and a pointer to a CompileUnit object identifying
// the containing compilation unit. It produces a token chain as output.
DBG_STOPPOINT,
// DEBUG_LOC - This node is used to represent source line information
// embedded in the code. It takes a token chain as input, then a line
// number, then a column then a file id (provided by MachineModuleInfo.) It
@ -625,7 +625,7 @@ namespace ISD {
// read / write specifier, and locality specifier.
PREFETCH,
// OUTCHAIN = MEMBARRIER(INCHAIN, load-load, load-store, store-load,
// OUTCHAIN = MEMBARRIER(INCHAIN, load-load, load-store, store-load,
// store-store, device)
// This corresponds to the memory.barrier intrinsic.
// it takes an input chain, 4 operands to specify the type of barrier, an
@ -659,7 +659,7 @@ namespace ISD {
ATOMIC_LOAD_MAX,
ATOMIC_LOAD_UMIN,
ATOMIC_LOAD_UMAX,
// BUILTIN_OP_END - This must be the last enum value in this list.
BUILTIN_OP_END
};
@ -682,9 +682,9 @@ namespace ISD {
/// isDebugLabel - Return true if the specified node represents a debug
/// label (i.e. ISD::DBG_LABEL or TargetInstrInfo::DBG_LABEL node).
bool isDebugLabel(const SDNode *N);
//===--------------------------------------------------------------------===//
/// MemIndexedMode enum - This enum defines the load / store indexed
/// MemIndexedMode enum - This enum defines the load / store indexed
/// addressing modes.
///
/// UNINDEXED "Normal" load / store. The effective address is already
@ -729,7 +729,7 @@ namespace ISD {
/// integer result type.
/// ZEXTLOAD loads the integer operand and zero extends it to a larger
/// integer result type.
/// EXTLOAD is used for three things: floating point extending loads,
/// EXTLOAD is used for three things: floating point extending loads,
/// integer extending loads [the top bits are undefined], and vector
/// extending loads [load into low elt].
///
@ -834,7 +834,7 @@ namespace ISD {
CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, bool isInteger);
//===--------------------------------------------------------------------===//
/// CvtCode enum - This enum defines the various converts CONVERT_RNDSAT
/// CvtCode enum - This enum defines the various converts CONVERT_RNDSAT
/// supports.
enum CvtCode {
CVT_FF, // Float from Float
@ -915,15 +915,15 @@ public:
inline unsigned getMachineOpcode() const;
inline const DebugLoc getDebugLoc() const;
/// reachesChainWithoutSideEffects - Return true if this operand (which must
/// be a chain) reaches the specified operand without crossing any
/// be a chain) reaches the specified operand without crossing any
/// side-effecting instructions. In practice, this looks through token
/// factors and non-volatile loads. In order to remain efficient, this only
/// looks a couple of nodes in, it does not do an exhaustive search.
bool reachesChainWithoutSideEffects(SDValue Dest,
bool reachesChainWithoutSideEffects(SDValue Dest,
unsigned Depth = 2) const;
/// use_empty - Return true if there are no nodes using value ResNo
/// of Node.
///
@ -937,10 +937,10 @@ public:
template<> struct DenseMapInfo<SDValue> {
static inline SDValue getEmptyKey() {
return SDValue((SDNode*)-1, -1U);
static inline SDValue getEmptyKey() {
return SDValue((SDNode*)-1, -1U);
}
static inline SDValue getTombstoneKey() {
static inline SDValue getTombstoneKey() {
return SDValue((SDNode*)-1, 0);
}
static unsigned getHashValue(const SDValue &Val) {
@ -978,7 +978,7 @@ class SDUse {
SDValue Val;
/// User - The user of this value.
SDNode *User;
/// Prev, Next - Pointers to the uses list of the SDNode referred by
/// Prev, Next - Pointers to the uses list of the SDNode referred by
/// this operand.
SDUse **Prev, *Next;
@ -994,7 +994,7 @@ public:
/// If implicit conversion to SDValue doesn't work, the get() method returns
/// the SDValue.
const SDValue &get() const { return Val; }
/// getUser - This returns the SDNode that contains this Use.
SDNode *getUser() { return User; }
@ -1012,7 +1012,7 @@ public:
bool operator==(const SDValue &V) const {
return Val == V;
}
/// operator!= - Convenience function for get().operator!=
bool operator!=(const SDValue &V) const {
return Val != V;
@ -1075,7 +1075,7 @@ private:
/// NodeType - The operation that this node performs.
///
short NodeType;
/// OperandsNeedDelete - This is true if OperandList was new[]'d. If true,
/// then they will be delete[]'d when the node is destroyed.
unsigned short OperandsNeedDelete : 1;
@ -1093,7 +1093,7 @@ private:
/// OperandList - The values that are used by this operation.
///
SDUse *OperandList;
/// ValueList - The types of the values this node defines. SDNode's may
/// define multiple values simultaneously.
const MVT *ValueList;
@ -1170,7 +1170,7 @@ public:
void setDebugLoc(const DebugLoc dl) { debugLoc = dl; }
/// use_iterator - This class provides iterator support for SDUse
/// operands that use a specific SDNode.
/// operands that use a specific SDNode.
class use_iterator
: public forward_iterator<SDUse, ptrdiff_t> {
SDUse *Op;
@ -1190,7 +1190,7 @@ public:
bool operator!=(const use_iterator &x) const {
return !operator==(x);
}
/// atEnd - return true if this iterator is at the end of uses list.
bool atEnd() const { return Op == 0; }
@ -1260,7 +1260,7 @@ public:
///
unsigned getNumOperands() const { return NumOperands; }
/// getConstantOperandVal - Helper method returns the integer value of a
/// getConstantOperandVal - Helper method returns the integer value of a
/// ConstantSDNode operand.
uint64_t getConstantOperandVal(unsigned Num) const;
@ -1353,7 +1353,7 @@ protected:
return Ret;
}
SDNode(unsigned Opc, const DebugLoc dl, SDVTList VTs, const SDValue *Ops,
SDNode(unsigned Opc, const DebugLoc dl, SDVTList VTs, const SDValue *Ops,
unsigned NumOps)
: NodeType(Opc), OperandsNeedDelete(true), SubclassData(0),
NodeId(-1),
@ -1374,7 +1374,7 @@ protected:
NodeId(-1), OperandList(0), ValueList(VTs.VTs), UseList(NULL),
NumOperands(0), NumValues(VTs.NumVTs),
debugLoc(dl) {}
/// InitOperands - Initialize the operands list of this with 1 operand.
void InitOperands(SDUse *Ops, const SDValue &Op0) {
Ops[0].setUser(this);
@ -1545,7 +1545,7 @@ public:
getSDVTList(MVT::Other)) {
InitOperands(&Op, X);
}
~HandleSDNode();
~HandleSDNode();
const SDValue &getValue() const { return Op; }
};
@ -1713,7 +1713,7 @@ class ConstantSDNode : public SDNode {
protected:
friend class SelectionDAG;
ConstantSDNode(bool isTarget, const ConstantInt *val, MVT VT)
: SDNode(isTarget ? ISD::TargetConstant : ISD::Constant,
: SDNode(isTarget ? ISD::TargetConstant : ISD::Constant,
DebugLoc::getUnknownLoc(), getSDVTList(VT)), Value(val) {
}
public:
@ -1752,7 +1752,7 @@ public:
/// two floating point values.
/// We leave the version with the double argument here because it's just so
/// convenient to write "2.0" and the like. Without this function we'd
/// convenient to write "2.0" and the like. Without this function we'd
/// have to duplicate its logic everywhere it's called.
bool isExactlyValue(double V) const {
bool ignored;
@ -1770,7 +1770,7 @@ public:
static bool classof(const ConstantFPSDNode *) { return true; }
static bool classof(const SDNode *N) {
return N->getOpcode() == ISD::ConstantFP ||
return N->getOpcode() == ISD::ConstantFP ||
N->getOpcode() == ISD::TargetConstantFP;
}
};
@ -1801,7 +1801,7 @@ class FrameIndexSDNode : public SDNode {
protected:
friend class SelectionDAG;
FrameIndexSDNode(int fi, MVT VT, bool isTarg)
: SDNode(isTarg ? ISD::TargetFrameIndex : ISD::FrameIndex,
: SDNode(isTarg ? ISD::TargetFrameIndex : ISD::FrameIndex,
DebugLoc::getUnknownLoc(), getSDVTList(VT)), FI(fi) {
}
public:
@ -1824,9 +1824,9 @@ protected:
DebugLoc::getUnknownLoc(), getSDVTList(VT)), JTI(jti) {
}
public:
int getIndex() const { return JTI; }
static bool classof(const JumpTableSDNode *) { return true; }
static bool classof(const SDNode *N) {
return N->getOpcode() == ISD::JumpTable ||
@ -1859,7 +1859,7 @@ protected:
}
ConstantPoolSDNode(bool isTarget, MachineConstantPoolValue *v,
MVT VT, int o=0)
: SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool,
: SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool,
DebugLoc::getUnknownLoc(),
getSDVTList(VT)), Offset(o), Alignment(0) {
assert((int)Offset >= 0 && "Offset is too large");
@ -1894,7 +1894,7 @@ public:
int getOffset() const {
return Offset & ~(1 << (sizeof(unsigned)*8-1));
}
// Return the alignment of this constant pool object, which is either 0 (for
// default alignment) or log2 of the desired value.
unsigned getAlignment() const { return Alignment; }
@ -2087,7 +2087,7 @@ protected:
friend class SelectionDAG;
explicit CvtRndSatSDNode(MVT VT, DebugLoc dl, const SDValue *Ops,
unsigned NumOps, ISD::CvtCode Code)
: SDNode(ISD::CONVERT_RNDSAT, dl, getSDVTList(VT), Ops, NumOps),
: SDNode(ISD::CONVERT_RNDSAT, dl, getSDVTList(VT), Ops, NumOps),
CvtCode(Code) {
assert(NumOps == 5 && "wrong number of operations");
}
@ -2150,14 +2150,14 @@ namespace ISD {
void setNest() { Flags |= One << NestOffs; }
unsigned getByValAlign() const {
return (unsigned)
return (unsigned)
((One << ((Flags & ByValAlign) >> ByValAlignOffs)) / 2);
}
void setByValAlign(unsigned A) {
Flags = (Flags & ~ByValAlign) |
(uint64_t(Log2_32(A) + 1) << ByValAlignOffs);
}
bool isSplit() const { return Flags & Split; }
void setSplit() { Flags |= One << SplitOffs; }
@ -2214,8 +2214,8 @@ class CallSDNode : public SDNode {
bool Inreg;
protected:
friend class SelectionDAG;
CallSDNode(unsigned cc, DebugLoc dl, bool isvararg, bool istailcall,
bool isinreg, SDVTList VTs, const SDValue *Operands,
CallSDNode(unsigned cc, DebugLoc dl, bool isvararg, bool istailcall,
bool isinreg, SDVTList VTs, const SDValue *Operands,
unsigned numOperands)
: SDNode(ISD::CALL, dl, VTs, Operands, numOperands),
CallingConv(cc), IsVarArg(isvararg), IsTailCall(istailcall),

784
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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File diff suppressed because it is too large Load Diff

710
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
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File diff suppressed because it is too large Load Diff

4
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
View File

@ -150,7 +150,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) {
SDValue Op2 = GetPromotedInteger(N->getOperand(2));
SDValue Op3 = GetPromotedInteger(N->getOperand(3));
SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
N->getMemoryVT(), N->getChain(), N->getBasePtr(),
Op2, Op3, N->getSrcValue(), N->getAlignment());
// Legalized the chain result - switch anything that used the old chain to
@ -2067,7 +2067,7 @@ void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
}
NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
LHSHi, RHSHi, ISD::SETEQ, false,
LHSHi, RHSHi, ISD::SETEQ, false,
DagCombineInfo, dl);
if (!NewLHS.getNode())
NewLHS = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),

8
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
View File

@ -126,7 +126,7 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_BIT_CONVERT(SDNode *N) {
SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) {
MVT NewVT = N->getValueType(0).getVectorElementType();
SDValue Op0 = GetScalarizedVector(N->getOperand(0));
return DAG.getConvertRndSat(NewVT, N->getDebugLoc(),
return DAG.getConvertRndSat(NewVT, N->getDebugLoc(),
Op0, DAG.getValueType(NewVT),
DAG.getValueType(Op0.getValueType()),
N->getOperand(3),
@ -544,7 +544,7 @@ void DAGTypeLegalizer::SplitVecRes_CONVERT_RNDSAT(SDNode *N, SDValue &Lo,
SDValue SatOp = N->getOperand(4);
ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
Lo = DAG.getConvertRndSat(LoVT, dl, VLo, DTyOpLo, STyOpLo, RndOp, SatOp,
Lo = DAG.getConvertRndSat(LoVT, dl, VLo, DTyOpLo, STyOpLo, RndOp, SatOp,
CvtCode);
Hi = DAG.getConvertRndSat(HiVT, dl, VHi, DTyOpHi, STyOpHi, RndOp, SatOp,
CvtCode);
@ -1227,7 +1227,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
if (InVTNumElts % WidenNumElts == 0) {
// Extract the input and convert the shorten input vector.
return DAG.getNode(Opcode, dl, WidenVT,
DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT,
DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT,
InOp, DAG.getIntPtrConstant(0)));
}
}
@ -1953,7 +1953,7 @@ SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) {
if (StChain.size() == 1)
return StChain[0];
else
return DAG.getNode(ISD::TokenFactor, dl,
return DAG.getNode(ISD::TokenFactor, dl,
MVT::Other,&StChain[0],StChain.size());
}

338
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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File diff suppressed because it is too large Load Diff

184
lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
View File

@ -338,7 +338,7 @@ void FunctionLoweringInfo::set(Function &fn, MachineFunction &mf,
unsigned SrcFile = DW->RecordSource(CU.getDirectory(),
CU.getFilename());
unsigned idx = MF->getOrCreateDebugLocID(SrcFile,
SPI->getLine(),
SPI->getLine(),
SPI->getColumn());
DL = DebugLoc::get(idx);
}
@ -360,7 +360,7 @@ void FunctionLoweringInfo::set(Function &fn, MachineFunction &mf,
DL = DebugLoc::get(MF->getOrCreateDebugLocID(SrcFile, Line, 0));
}
}
break;
}
}
@ -463,7 +463,7 @@ static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl,
// Assemble the trailing non-power-of-2 part.
unsigned OddParts = NumParts - RoundParts;
MVT OddVT = MVT::getIntegerVT(OddParts * PartBits);
Hi = getCopyFromParts(DAG, dl,
Hi = getCopyFromParts(DAG, dl,
Parts+RoundParts, OddParts, PartVT, OddVT);
// Combine the round and odd parts.
@ -646,7 +646,7 @@ static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, SDValue Val,
// The number of parts is a power of 2. Repeatedly bisect the value using
// EXTRACT_ELEMENT.
Parts[0] = DAG.getNode(ISD::BIT_CONVERT, dl,
Parts[0] = DAG.getNode(ISD::BIT_CONVERT, dl,
MVT::getIntegerVT(ValueVT.getSizeInBits()),
Val);
for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
@ -656,17 +656,17 @@ static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, SDValue Val,
SDValue &Part0 = Parts[i];
SDValue &Part1 = Parts[i+StepSize/2];
Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
ThisVT, Part0,
DAG.getConstant(1, PtrVT));
Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
ThisVT, Part0,
DAG.getConstant(0, PtrVT));
if (ThisBits == PartBits && ThisVT != PartVT) {
Part0 = DAG.getNode(ISD::BIT_CONVERT, dl,
Part0 = DAG.getNode(ISD::BIT_CONVERT, dl,
PartVT, Part0);
Part1 = DAG.getNode(ISD::BIT_CONVERT, dl,
Part1 = DAG.getNode(ISD::BIT_CONVERT, dl,
PartVT, Part1);
}
}
@ -687,7 +687,7 @@ static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, SDValue Val,
assert(ValueVT.getVectorElementType() == PartVT &&
ValueVT.getVectorNumElements() == 1 &&
"Only trivial vector-to-scalar conversions should get here!");
Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
PartVT, Val,
DAG.getConstant(0, PtrVT));
}
@ -713,12 +713,12 @@ static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, SDValue Val,
SmallVector<SDValue, 8> Ops(NumIntermediates);
for (unsigned i = 0; i != NumIntermediates; ++i)
if (IntermediateVT.isVector())
Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl,
Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl,
IntermediateVT, Val,
DAG.getConstant(i * (NumElements / NumIntermediates),
PtrVT));
else
Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
IntermediateVT, Val,
DAG.getConstant(i, PtrVT));
@ -935,7 +935,7 @@ SDValue SelectionDAGLowering::getValue(const Value *V) {
}
// Create a BUILD_VECTOR node.
return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
VT, &Ops[0], Ops.size());
}
@ -959,7 +959,7 @@ SDValue SelectionDAGLowering::getValue(const Value *V) {
void SelectionDAGLowering::visitRet(ReturnInst &I) {
if (I.getNumOperands() == 0) {
DAG.setRoot(DAG.getNode(ISD::RET, getCurDebugLoc(),
DAG.setRoot(DAG.getNode(ISD::RET, getCurDebugLoc(),
MVT::Other, getControlRoot()));
return;
}
@ -1250,7 +1250,7 @@ void SelectionDAGLowering::visitBr(BranchInst &I) {
// If this is not a fall-through branch, emit the branch.
if (Succ0MBB != NextBlock)
DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
MVT::Other, getControlRoot(),
DAG.getBasicBlock(Succ0MBB)));
return;
@ -1344,7 +1344,7 @@ void SelectionDAGLowering::visitSwitchCase(CaseBlock &CB) {
MVT VT = CmpOp.getValueType();
if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
ISD::SETLE);
} else {
SDValue SUB = DAG.getNode(ISD::SUB, dl,
@ -1401,7 +1401,7 @@ void SelectionDAGLowering::visitJumpTable(JumpTable &JT) {
SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
JT.Reg, PTy);
SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
DAG.setRoot(DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
DAG.setRoot(DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
MVT::Other, Index.getValue(1),
Table, Index));
}
@ -1424,10 +1424,10 @@ void SelectionDAGLowering::visitJumpTableHeader(JumpTable &JT,
// This value may be smaller or larger than the target's pointer type, and
// therefore require extension or truncating.
if (VT.bitsGT(TLI.getPointerTy()))
SwitchOp = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
SwitchOp = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
TLI.getPointerTy(), SUB);
else
SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
TLI.getPointerTy(), SUB);
unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
@ -1478,10 +1478,10 @@ void SelectionDAGLowering::visitBitTestHeader(BitTestBlock &B) {
SDValue ShiftOp;
if (VT.bitsGT(TLI.getPointerTy()))
ShiftOp = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
ShiftOp = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
TLI.getPointerTy(), SUB);
else
ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
TLI.getPointerTy(), SUB);
B.Reg = FuncInfo.MakeReg(TLI.getPointerTy());
@ -1518,13 +1518,13 @@ void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
// Make desired shift
SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), Reg,
TLI.getPointerTy());
SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(),
SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(),
TLI.getPointerTy(),
DAG.getConstant(1, TLI.getPointerTy()),
ShiftOp);
// Emit bit tests and jumps
SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
TLI.getPointerTy(), SwitchVal,
DAG.getConstant(B.Mask, TLI.getPointerTy()));
SDValue AndCmp = DAG.getSetCC(getCurDebugLoc(),
@ -1577,7 +1577,7 @@ void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
CurMBB->addSuccessor(LandingPad);
// Drop into normal successor.
DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
MVT::Other, getControlRoot(),
DAG.getBasicBlock(Return)));
}
@ -2144,7 +2144,7 @@ void SelectionDAGLowering::visitSub(User &I) {
Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
if (CV == CNZ) {
SDValue Op2 = getValue(I.getOperand(1));
setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
Op2.getValueType(), Op2));
return;
}
@ -2155,7 +2155,7 @@ void SelectionDAGLowering::visitSub(User &I) {
if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
SDValue Op2 = getValue(I.getOperand(1));
setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
Op2.getValueType(), Op2));
return;
}
@ -2168,7 +2168,7 @@ void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
SDValue Op1 = getValue(I.getOperand(0));
SDValue Op2 = getValue(I.getOperand(1));
setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
Op1.getValueType(), Op1, Op2));
}
@ -2177,14 +2177,14 @@ void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
SDValue Op2 = getValue(I.getOperand(1));
if (!isa<VectorType>(I.getType())) {
if (TLI.getPointerTy().bitsLT(Op2.getValueType()))
Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
TLI.getPointerTy(), Op2);
else if (TLI.getPointerTy().bitsGT(Op2.getValueType()))
Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
TLI.getPointerTy(), Op2);
}
setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
Op1.getValueType(), Op1, Op2));
}
@ -2221,7 +2221,7 @@ void SelectionDAGLowering::visitVICmp(User &I) {
SDValue Op1 = getValue(I.getOperand(0));
SDValue Op2 = getValue(I.getOperand(1));
ISD::CondCode Opcode = getICmpCondCode(predicate);
setValue(&I, DAG.getVSetCC(getCurDebugLoc(), Op1.getValueType(),
setValue(&I, DAG.getVSetCC(getCurDebugLoc(), Op1.getValueType(),
Op1, Op2, Opcode));
}
@ -2250,12 +2250,12 @@ void SelectionDAGLowering::visitSelect(User &I) {
SDValue FalseVal = getValue(I.getOperand(2));
for (unsigned i = 0; i != NumValues; ++i)
Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(),
Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(),
TrueVal.getValueType(), Cond,
SDValue(TrueVal.getNode(), TrueVal.getResNo() + i),
SDValue(FalseVal.getNode(), FalseVal.getResNo() + i));
setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
DAG.getVTList(&ValueVTs[0], NumValues),
&Values[0], NumValues));
}
@ -2289,7 +2289,7 @@ void SelectionDAGLowering::visitFPTrunc(User &I) {
// FPTrunc is never a no-op cast, no need to check
SDValue N = getValue(I.getOperand(0));
MVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
DestVT, N, DAG.getIntPtrConstant(0)));
}
@ -2353,7 +2353,7 @@ void SelectionDAGLowering::visitIntToPtr(User &I) {
setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
else
// Note: ZERO_EXTEND can handle cases where the sizes are equal too
setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
DestVT, N));
}
@ -2364,7 +2364,7 @@ void SelectionDAGLowering::visitBitCast(User &I) {
// BitCast assures us that source and destination are the same size so this
// is either a BIT_CONVERT or a no-op.
if (DestVT != N.getValueType())
setValue(&I, DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
setValue(&I, DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
DestVT, N)); // convert types
else
setValue(&I, N); // noop cast.
@ -2373,18 +2373,18 @@ void SelectionDAGLowering::visitBitCast(User &I) {
void SelectionDAGLowering::visitInsertElement(User &I) {
SDValue InVec = getValue(I.getOperand(0));
SDValue InVal = getValue(I.getOperand(1));
SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
TLI.getPointerTy(),
getValue(I.getOperand(2)));
setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
TLI.getValueType(I.getType()),
InVec, InVal, InIdx));
}
void SelectionDAGLowering::visitExtractElement(User &I) {
SDValue InVec = getValue(I.getOperand(0));
SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
TLI.getPointerTy(),
getValue(I.getOperand(1)));
setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
@ -2417,7 +2417,7 @@ void SelectionDAGLowering::visitShuffleVector(User &I) {
int SrcNumElts = SrcVT.getVectorNumElements();
if (SrcNumElts == MaskNumElts) {
setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, getCurDebugLoc(),
setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, getCurDebugLoc(),
VT, Src1, Src2, Mask));
return;
}
@ -2431,7 +2431,7 @@ void SelectionDAGLowering::visitShuffleVector(User &I) {
// lengths match.
if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) {
// The shuffle is concatenating two vectors together.
setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
VT, Src1, Src2));
return;
}
@ -2448,9 +2448,9 @@ void SelectionDAGLowering::visitShuffleVector(User &I) {
MOps1[i] = UndefVal;
MOps2[i] = UndefVal;
}
Src1 = DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
Src1 = DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
VT, MOps1, NumConcat);
Src2 = DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
Src2 = DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
VT, MOps2, NumConcat);
delete [] MOps1;
@ -2470,11 +2470,11 @@ void SelectionDAGLowering::visitShuffleVector(User &I) {
MaskEltVT));
}
}
Mask = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
Mask = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
Mask.getValueType(),
&MappedOps[0], MappedOps.size());
setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, getCurDebugLoc(),
setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, getCurDebugLoc(),
VT, Src1, Src2, Mask));
return;
}
@ -2570,10 +2570,10 @@ void SelectionDAGLowering::visitShuffleVector(User &I) {
}
}
}
Mask = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
Mask = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
Mask.getValueType(),
&MappedOps[0], MappedOps.size());
setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, getCurDebugLoc(),
setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, getCurDebugLoc(),
VT, Src1, Src2, Mask));
return;
}
@ -2597,11 +2597,11 @@ void SelectionDAGLowering::visitShuffleVector(User &I) {
EltVT, Src1, DAG.getConstant(Idx, PtrVT)));
else
Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
EltVT, Src2,
EltVT, Src2,
DAG.getConstant(Idx - SrcNumElts, PtrVT)));
}
}
setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
VT, &Ops[0], Ops.size()));
}
@ -2641,7 +2641,7 @@ void SelectionDAGLowering::visitInsertValue(InsertValueInst &I) {
Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
SDValue(Agg.getNode(), Agg.getResNo() + i);
setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
DAG.getVTList(&AggValueVTs[0], NumAggValues),
&Values[0], NumAggValues));
}
@ -2669,7 +2669,7 @@ void SelectionDAGLowering::visitExtractValue(ExtractValueInst &I) {
DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
SDValue(Agg.getNode(), Agg.getResNo() + i);
setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
DAG.getVTList(&ValValueVTs[0], NumValValues),
&Values[0], NumValValues));
}
@ -2719,10 +2719,10 @@ void SelectionDAGLowering::visitGetElementPtr(User &I) {
// If the index is smaller or larger than intptr_t, truncate or extend
// it.
if (IdxN.getValueType().bitsLT(N.getValueType()))
IdxN = DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(),
IdxN = DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(),
N.getValueType(), IdxN);
else if (IdxN.getValueType().bitsGT(N.getValueType()))
IdxN = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
IdxN = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
N.getValueType(), IdxN);
// If this is a multiply by a power of two, turn it into a shl
@ -2730,17 +2730,17 @@ void SelectionDAGLowering::visitGetElementPtr(User &I) {
if (ElementSize != 1) {
if (isPowerOf2_64(ElementSize)) {
unsigned Amt = Log2_64(ElementSize);
IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
N.getValueType(), IdxN,
DAG.getConstant(Amt, TLI.getPointerTy()));
} else {
SDValue Scale = DAG.getIntPtrConstant(ElementSize);
IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
N.getValueType(), IdxN, Scale);
}
}
N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
N.getValueType(), N, IdxN);
}
}
@ -2762,10 +2762,10 @@ void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
SDValue AllocSize = getValue(I.getArraySize());
MVT IntPtr = TLI.getPointerTy();
if (IntPtr.bitsLT(AllocSize.getValueType()))
AllocSize = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
AllocSize = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
IntPtr, AllocSize);
else if (IntPtr.bitsGT(AllocSize.getValueType()))
AllocSize = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
AllocSize = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
IntPtr, AllocSize);
AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr, AllocSize,
@ -2781,18 +2781,18 @@ void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
// Round the size of the allocation up to the stack alignment size
// by add SA-1 to the size.
AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
AllocSize.getValueType(), AllocSize,
DAG.getIntPtrConstant(StackAlign-1));
// Mask out the low bits for alignment purposes.
AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
AllocSize.getValueType(), AllocSize,
DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
const MVT *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
MVT::Other);
SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
VTs, 2, Ops, 3);
setValue(&I, DSA);
DAG.setRoot(DSA.getValue(1));
@ -2836,7 +2836,7 @@ void SelectionDAGLowering::visitLoad(LoadInst &I) {
MVT PtrVT = Ptr.getValueType();
for (unsigned i = 0; i != NumValues; ++i) {
SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
DAG.getNode(ISD::ADD, getCurDebugLoc(),
DAG.getNode(ISD::ADD, getCurDebugLoc(),
PtrVT, Ptr,
DAG.getConstant(Offsets[i], PtrVT)),
SV, Offsets[i],
@ -2846,7 +2846,7 @@ void SelectionDAGLowering::visitLoad(LoadInst &I) {
}
if (!ConstantMemory) {
SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
MVT::Other,
&Chains[0], NumValues);
if (isVolatile)
@ -2855,7 +2855,7 @@ void SelectionDAGLowering::visitLoad(LoadInst &I) {
PendingLoads.push_back(Chain);
}
setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
DAG.getVTList(&ValueVTs[0], NumValues),
&Values[0], NumValues));
}
@ -2886,13 +2886,13 @@ void SelectionDAGLowering::visitStore(StoreInst &I) {
for (unsigned i = 0; i != NumValues; ++i)
Chains[i] = DAG.getStore(Root, getCurDebugLoc(),
SDValue(Src.getNode(), Src.getResNo() + i),
DAG.getNode(ISD::ADD, getCurDebugLoc(),
DAG.getNode(ISD::ADD, getCurDebugLoc(),
PtrVT, Ptr,
DAG.getConstant(Offsets[i], PtrVT)),
PtrV, Offsets[i],
isVolatile, Alignment);
DAG.setRoot(DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
DAG.setRoot(DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
MVT::Other, &Chains[0], NumValues));
}
@ -2961,15 +2961,15 @@ void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
Info.readMem, Info.writeMem);
}
else if (!HasChain)
Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
VTList, VTs.size(),
&Ops[0], Ops.size());
else if (I.getType() != Type::VoidTy)
Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
VTList, VTs.size(),
&Ops[0], Ops.size());
else
Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
VTList, VTs.size(),
&Ops[0], Ops.size());
@ -3121,7 +3121,7 @@ SelectionDAGLowering::implVisitAluOverflow(CallInst &I, ISD::NodeType Op) {
MVT ValueVTs[] = { Op1.getValueType(), MVT::i1 };
SDValue Ops[] = { Op1, Op2 };
SDValue Result = DAG.getNode(Op, getCurDebugLoc(),
SDValue Result = DAG.getNode(Op, getCurDebugLoc(),
DAG.getVTList(&ValueVTs[0], 2), &Ops[0], 2);
setValue(&I, Result);
@ -3235,7 +3235,7 @@ SelectionDAGLowering::visitExp(CallInst &I) {
SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
getF32Constant(DAG, 0x3f800000));
SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,
SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,
MVT::i32, t13);
// Add the exponent into the result in integer domain.
@ -3291,7 +3291,7 @@ SelectionDAGLowering::visitLog(CallInst &I) {
SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
getF32Constant(DAG, 0x3f949a29));
result = DAG.getNode(ISD::FADD, dl,
result = DAG.getNode(ISD::FADD, dl,
MVT::f32, LogOfExponent, LogOfMantissa);
} else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
// For floating-point precision of 12:
@ -3317,7 +3317,7 @@ SelectionDAGLowering::visitLog(CallInst &I) {
SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
getF32Constant(DAG, 0x3fdef31a));
result = DAG.getNode(ISD::FADD, dl,
result = DAG.getNode(ISD::FADD, dl,
MVT::f32, LogOfExponent, LogOfMantissa);
} else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
// For floating-point precision of 18:
@ -3351,7 +3351,7 @@ SelectionDAGLowering::visitLog(CallInst &I) {
SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
getF32Constant(DAG, 0x4006dcab));
result = DAG.getNode(ISD::FADD, dl,
result = DAG.getNode(ISD::FADD, dl,
MVT::f32, LogOfExponent, LogOfMantissa);
}
} else {
@ -3399,7 +3399,7 @@ SelectionDAGLowering::visitLog2(CallInst &I) {
SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
getF32Constant(DAG, 0x3fd6633d));
result = DAG.getNode(ISD::FADD, dl,
result = DAG.getNode(ISD::FADD, dl,
MVT::f32, LogOfExponent, Log2ofMantissa);
} else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
// For floating-point precision of 12:
@ -3425,7 +3425,7 @@ SelectionDAGLowering::visitLog2(CallInst &I) {
SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
getF32Constant(DAG, 0x4020d29c));
result = DAG.getNode(ISD::FADD, dl,
result = DAG.getNode(ISD::FADD, dl,
MVT::f32, LogOfExponent, Log2ofMantissa);
} else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
// For floating-point precision of 18:
@ -3460,7 +3460,7 @@ SelectionDAGLowering::visitLog2(CallInst &I) {
SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
getF32Constant(DAG, 0x4042902c));
result = DAG.getNode(ISD::FADD, dl,
result = DAG.getNode(ISD::FADD, dl,
MVT::f32, LogOfExponent, Log2ofMantissa);
}
} else {
@ -3510,7 +3510,7 @@ SelectionDAGLowering::visitLog10(CallInst &I) {
SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
getF32Constant(DAG, 0x3f011300));
result = DAG.getNode(ISD::FADD, dl,
result = DAG.getNode(ISD::FADD, dl,
MVT::f32, LogOfExponent, Log10ofMantissa);
} else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
// For floating-point precision of 12:
@ -3532,7 +3532,7 @@ SelectionDAGLowering::visitLog10(CallInst &I) {
SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
getF32Constant(DAG, 0x3f25f7c3));
result = DAG.getNode(ISD::FADD, dl,
result = DAG.getNode(ISD::FADD, dl,
MVT::f32, LogOfExponent, Log10ofMantissa);
} else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
// For floating-point precision of 18:
@ -3562,7 +3562,7 @@ SelectionDAGLowering::visitLog10(CallInst &I) {
SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
getF32Constant(DAG, 0x3f57ce70));
result = DAG.getNode(ISD::FADD, dl,
result = DAG.getNode(ISD::FADD, dl,
MVT::f32, LogOfExponent, Log10ofMantissa);
}
} else {
@ -3615,7 +3615,7 @@ SelectionDAGLowering::visitExp2(CallInst &I) {
SDValue TwoToFractionalPartOfX =
DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
result = DAG.getNode(ISD::BIT_CONVERT, dl,
result = DAG.getNode(ISD::BIT_CONVERT, dl,
MVT::f32, TwoToFractionalPartOfX);
} else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
// For floating-point precision of 12:
@ -3640,7 +3640,7 @@ SelectionDAGLowering::visitExp2(CallInst &I) {
SDValue TwoToFractionalPartOfX =
DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
result = DAG.getNode(ISD::BIT_CONVERT, dl,
result = DAG.getNode(ISD::BIT_CONVERT, dl,
MVT::f32, TwoToFractionalPartOfX);
} else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
// For floating-point precision of 18:
@ -3676,7 +3676,7 @@ SelectionDAGLowering::visitExp2(CallInst &I) {
SDValue TwoToFractionalPartOfX =
DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
result = DAG.getNode(ISD::BIT_CONVERT, dl,
result = DAG.getNode(ISD::BIT_CONVERT, dl,
MVT::f32, TwoToFractionalPartOfX);
}
} else {
@ -3773,7 +3773,7 @@ SelectionDAGLowering::visitPow(CallInst &I) {
SDValue TwoToFractionalPartOfX =
DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
result = DAG.getNode(ISD::BIT_CONVERT, dl,
result = DAG.getNode(ISD::BIT_CONVERT, dl,
MVT::f32, TwoToFractionalPartOfX);
} else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
// For floating-point precision of 18:
@ -3809,7 +3809,7 @@ SelectionDAGLowering::visitPow(CallInst &I) {
SDValue TwoToFractionalPartOfX =
DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
result = DAG.getNode(ISD::BIT_CONVERT, dl,
result = DAG.getNode(ISD::BIT_CONVERT, dl,
MVT::f32, TwoToFractionalPartOfX);
}
} else {
@ -3903,7 +3903,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
unsigned SrcFile = DW->RecordSource(CU.getDirectory(), CU.getFilename());
unsigned idx = DAG.getMachineFunction().
getOrCreateDebugLocID(SrcFile,
SPI.getLine(),
SPI.getLine(),
SPI.getColumn());
setCurDebugLoc(DebugLoc::get(idx));
}
@ -4477,7 +4477,7 @@ void SelectionDAGLowering::visitCall(CallInst &I) {
I.getType() == I.getOperand(2)->getType()) {
SDValue LHS = getValue(I.getOperand(1));
SDValue RHS = getValue(I.getOperand(2));
setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
LHS.getValueType(), LHS, RHS));
return;
}
@ -4489,7 +4489,7 @@ void SelectionDAGLowering::visitCall(CallInst &I) {
I.getOperand(1)->getType()->isFloatingPoint() &&
I.getType() == I.getOperand(1)->getType()) {
SDValue Tmp = getValue(I.getOperand(1));
setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(),
setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(),
Tmp.getValueType(), Tmp));
return;
}
@ -4501,7 +4501,7 @@ void SelectionDAGLowering::visitCall(CallInst &I) {
I.getOperand(1)->getType()->isFloatingPoint() &&
I.getType() == I.getOperand(1)->getType()) {
SDValue Tmp = getValue(I.getOperand(1));
setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(),
setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(),
Tmp.getValueType(), Tmp));
return;
}
@ -4513,7 +4513,7 @@ void SelectionDAGLowering::visitCall(CallInst &I) {
I.getOperand(1)->getType()->isFloatingPoint() &&
I.getType() == I.getOperand(1)->getType()) {
SDValue Tmp = getValue(I.getOperand(1));
setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(),
setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(),
Tmp.getValueType(), Tmp));
return;
}
@ -4606,7 +4606,7 @@ SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
Parts[i] = P;
}
Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
NumRegs, RegisterVT, ValueVT);
Part += NumRegs;
Parts.clear();
@ -5370,7 +5370,7 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
// If this asm returns a register value, copy the result from that register
// and set it as the value of the call.
if (!RetValRegs.Regs.empty()) {
SDValue Val = RetValRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
SDValue Val = RetValRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
Chain, &Flag);
// FIXME: Why don't we do this for inline asms with MRVs?
@ -5817,7 +5817,7 @@ LowerArguments(BasicBlock *LLVMBB) {
ComputeValueVTs(TLI, AI->getType(), ValueVTs);
unsigned NumValues = ValueVTs.size();
if (!AI->use_empty()) {
SDL->setValue(AI, SDL->DAG.getMergeValues(&Args[a], NumValues,
SDL->setValue(AI, SDL->DAG.getMergeValues(&Args[a], NumValues,
SDL->getCurDebugLoc()));
// If this argument is live outside of the entry block, insert a copy from
// whereever we got it to the vreg that other BB's will reference it as.

688
lib/Target/PowerPC/PPCISelLowering.cpp
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502
lib/Target/X86/X86ISelLowering.cpp
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File diff suppressed because it is too large Load Diff