6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-08-23 17:29:19 +00:00
Code Issues Projects Releases Wiki Activity

Move getNextOperandForReg() into MachineRegisterInfo.

Browse Source 
MRI provides iterators for traversing the use-def chains. They should
not be accessible from anywhere else.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161543 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2012-08-08 23:44:07 +00:00
parent 0c5f5f4916
commit fdd6484b41
2 changed files with 14 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
include/llvm/CodeGen/MachineOperand.h
View File

@ -138,6 +138,9 @@ private:
/// This is valid for all operand types, when the operand is in an instr.
MachineInstr *ParentMI;
// MRI accesses Contents.Reg directly.
friend class MachineRegisterInfo;
/// Contents union - This contains the payload for the various operand types.
union {
MachineBasicBlock *MBB; // For MO_MachineBasicBlock.
@ -305,15 +308,6 @@ public:
return !isUndef() && !isInternalRead() && (isUse() || getSubReg());
}
/// getNextOperandForReg - Return the next MachineOperand in the linked list
/// of operands that use or define the same register.
/// Don't call this function directly, see the def-use iterators in
/// MachineRegisterInfo instead.
MachineOperand *getNextOperandForReg() const {
assert(isReg() && "This is not a register operand!");
return Contents.Reg.Next;
}
//===--------------------------------------------------------------------===//
// Mutators for Register Operands
//===--------------------------------------------------------------------===//

13
include/llvm/CodeGen/MachineRegisterInfo.h
View File

@ -57,6 +57,12 @@ class MachineRegisterInfo {
/// physical registers.
MachineOperand **PhysRegUseDefLists;
/// Get the next element in the use-def chain.
static MachineOperand *getNextOperandForReg(const MachineOperand *MO) {
assert(MO && MO->isReg() && "This is not a register operand!");
return MO->Contents.Reg.Next;
}
/// UsedPhysRegs - This is a bit vector that is computed and set by the
/// register allocator, and must be kept up to date by passes that run after
/// register allocation (though most don't modify this). This is used
@ -135,6 +141,9 @@ public:
template<bool Uses, bool Defs, bool SkipDebug>
class defusechain_iterator;
// Make it a friend so it can access getNextOperandForReg().
template<bool, bool, bool> friend class defusechain_iterator;
/// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified
/// register.
typedef defusechain_iterator<true,true,false> reg_iterator;
@ -500,13 +509,13 @@ public:
// Iterator traversal: forward iteration only
defusechain_iterator &operator++() { // Preincrement
assert(Op && "Cannot increment end iterator!");
Op = Op->getNextOperandForReg();
Op = getNextOperandForReg(Op);
// If this is an operand we don't care about, skip it.
while (Op && ((!ReturnUses && Op->isUse()) ||
(!ReturnDefs && Op->isDef()) ||
(SkipDebug && Op->isDebug())))
Op = Op->getNextOperandForReg();
Op = getNextOperandForReg(Op);
return *this;
}